3.

Microprocessor Subsystem

3.1

CPUs

3.1.1

E51 Monitor Core

The E51 monitor core is a 64-bit embedded RISC-V CPU, including an instruction fetch unit, an execution pipeline,

and a data memory system. The monitor core supports the standard RISC-V RV64IMAC user-level instruction set,

with machine and user privilege modes. The E51 monitor core typically runs a bare metal code called Hart Software

Services.

Table 3-1. E51 Monitor Core

Feature

Description

ISA

RV64IMAC

Instruction cache

16 KB two way

Data tightly integrated memory

8 KB

ECC support

Single-error correct, double-error detect on the DTIM

Privilege modes

Machine (M), User (U)

3.1.1.1

Hart Software Services (HSS)

The Hart Software Services is a bare metal code that is built over the PolarFire SoC Hardware Abstraction Layer

(HAL). The HSS functions as a zero stage bootloader for bare metal, RTOS, SMP Linux, and AMP systems. It also

configures the MSS for peripheral selection, DDR configuration, L2 memory subsystem configuration, fabric interface

controllers, clocks, IO configuration, physical memory protection, and so on, with the configuration set by the MSS

configurator tool.

The HSS also enables inter-core communication as well as handles interfacing with the system controller for system

services. The HSS is designed to run on the E51 core and is available as open source.

3.1.1.2

E51 Instruction Fetch Unit

The E51 instruction fetch unit consists of a two-way, 16 KB instruction cache that supports 64-byte cache lines.

The access latency is one clock cycle. Writes to memory may be synchronized with the instruction fetch stream

with a FENCE.I instruction. The branch predictor comprises a branch target buffer (BTB), which predicts the target

of taken branches and jumps; a branch history table (BHT), which predicts the direction of conditional branches;

and a return-address stack (RAS), which predicts the target of procedure returns. The BTB is configured to hold 40

entries. The RAS is configured to hold two entries. The BHT uses a gshare prediction scheme with 7 bits of global

history to access an array of 128, two-bit saturating counters. The branch predictor has a one-cycle latency, so that

correctly predicted control-flow instructions result in no penalty. The branch predictor can be turned off during device

configuration to create deterministic systems.

3.1.1.3

E51 I-Cache Reconfiguration

The instruction cache can be partially reconfigured into an Instruction Tightly Integrated Memory (ITIM), which

occupies a fixed address range in the memory map. ITIM provides high performance, predictable instruction delivery.

Fetching an instruction from ITIM is as fast as an instruction-cache hit, with no possibility of a cache miss. ITIM can

hold data as well as instructions, though loads and stores to ITIM are not as performant as loads and stores to DTIM.

The instruction cache can be configured as ITIM for all ways except for 1 in units of cache lines (64 bytes). A single

cache way must remain as an instruction cache. ITIM is allocated simply by storing to it. A store to the nth byte of

the ITIM memory map reallocates the first n+1 bytes of instruction cache as ITIM, rounded up to the next cache line.

ITIM is deallocated by storing zero to the first byte after the ITIM region. The deallocated ITIM space is automatically

returned to the instruction cache. For determinism, software must clear the contents of ITIM after allocating it. It is

unpredictable whether ITIM contents are preserved between deallocation and allocation. ITIM is typically used for

reduced latency requirements like for an ISR.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 10