• Single-wire half-duplex mode in which Tx pad can be used for bi-directional data transfer

• Local interconnect network (LIN) header detection and auto baud rate calculation

• Communication with ISO 7816 smart cards

• Fractional baud rate capability

• Return to Zero Inverted (RZI) mod/demod blocks that allow infrared data association (IrDA) and serial infrared

(SIR) communications

• The most significant bit (MSB) or the least significant bit (LSB) as the first bit while sending or receiving data

3.5.9

I2C

Philips inter-integrated circuit (I2C) is a two-wire serial bus interface that provides data transfer between many

devices. PolarFire SoC contains two identical I2C peripherals in the MSS that provide a mechanism for serial

communication between the PolarFire SoC and external I2C compliant devices. I2C peripherals support the following

features:

• Master and Slave modes

• 7-bit addressing format and data transfers up to 100 Kbps in Standard mode and up to 400 Kbps in Fast mode

• Multi-master collision detection and arbitration

• Own slave address and general call address detection

• Second slave address detection

• System management bus (SMBus) timeout and real-time idle condition counters

• Input glitch or spike filters

3.5.10

Real Time Counter

PolarFire SoC integrates a real time calendar with built-in clock prescaler and an alarm wake-up comparator. It has

the following two modes of operation.

• Real time Calendar (counts seconds, minutes, hours, days, weeks, months, and years)

• Binary counter (counts from 0 to 243)

3.5.11

Watchdog Timer

There are five watchdogs in the MSS, one per CPU. The watchdog guards against system crashes by requiring that

it is regularly serviced by the assigned processor. The watchdog is not enabled at reset and generates a NMI upon

reaching the trigger value. Once enabled, the watchdog cannot be disabled.

3.5.12

Timer

The PolarFire SoC system timer consists of two programmable 32-bit decrement counters that generate interrupts to

the MSS and FPGA fabric. The two 32-bit timers are identical and have the following features.

• One-shot mode

• Periodic mode

• Concatenation mode in which two 32-bit timers can be concatenated to create a 64-bit timer

• Option to enable or disable the interrupt requests when timer reaches zero

• Controls to start, stop, and reset the timer

3.6

Processor-to-Fabric Interconnect

The interconnect between the FPGA fabric and the MSS switches are either AXI- or APB-based. There are three AXI

64-bit interfaces. Two interfaces support a full, 64-bit AXI bus into the fabric from the MSS and from the fabric to the

MSS. One AXI 64-bit interface supports a full, 64-bit AXI bus from the fabric into the MSS. The AXI buses all have

DLLs to cancel out any insertion delay and can operate asynchronously to the processors operating frequency. In

addition, a 32-bit APB bus is provided to the fabric from the MSS.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 23