• Two I2C

• MSS GPIO

System registers are available to select the signals connected to different IOs.

All these IOs are bonded out to pins in all PolarFire SoC packages.

For more details on MSS IOs, see the PolarFire SoC MSS Technical Reference Manual.

3.5.1

Gigabit Ethernet MAC

PolarFire SoC contains two identical Gigabit Ethernet MACs (GEM) integrated into the MSS. Each MAC can contain

a maximum frame length of 10,240 bytes that are SECDED protected. Additionally, the GEM supports a built-in

packet buffer DMA. Each GEM supports the following IEEE

® 802 standards:

• IEEE 802.3br Frame Pre-Emption (or Interspersing Express Traffic)

• IEEE 802.1Qci Receive (Ingress) Traffic Policing

• IEEE 802.1Qbb Priority-Based Flow Control

• IEEE 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames

• IEEE 802.1AS

• IEEE 802.1Qav

• IEEE 802.1Qbv

• IEEE 1588-2002 (v1), IEEE 1588-2008 (v1 and v2)

• IEEE 802.1CB Frame Redundancy and Elimination

3.5.1.1

PHY Interfaces

Each GEM is configured to simultaneously support TBI and GMII/MII modes. When using TBI, the PCS block of the

MAC is used, but not as an IEEE802.3X interface to a transceiver, but rather, is fed into a dedicated MSS SERDES

block and from there, interfaces to a PHY. This serialized interface between MAC and PHY is known as SGMII and is

part of the MSS. In SGMII mode, the PCS interface and the link speed auto-negotiation blocks are re-purposed from

their 802.3X function and are instead used to convey control information related to the MAC-PHY interface.

3.5.1.1.1 Direct SGMII I/O

The following functionality provides an SGMII interface from the GEM to the built-in MSS SGMII PHY:

• Clock Domain Recovery (CDR) of received 125 MHz clock

• Serializing/De-serializing

• PLL for synthesis of a 125 MHz transmit clock

• I/O buffers (four I/Os per MAC instance) allowing for differential transmit and receive data pairs

Note:  It is not possible to support the SyncE protocol when using the direct MSS SGMII interface.

3.5.1.1.2 GMII/MII To FPGA Fabric

A GMII/MII interface is provided between each MAC and the FPGA fabric to provide flexibility. In particular, it allows:

• Connecting to a FPGA fabric transceiver channel to provide an SGMII interface. Note that in this case, the

transceiver would be configured to perform 8b10b encoding/decoding in its PCS. This particular approach to

implementing an SGMII interface differs from the direct hard SGMII interface of the MSS in that it allows support

of the SyncE protocol, which is often used in conjunction with IEEE 1588.

3.5.1.1.3 PHY Management

Each MAC has an MDC output and an MDIO input and output port, which may be brought out separately for each

MAC instance within the MSS either to MSSIO or to the FPGA fabric. If desired, however, the user could bring out

only one management interface (and not use the second), as it is possible to control multiple PHYs using the one

interface (if hardware separation is not required).

3.5.1.2

MSS Receive Filtering

3.5.1.2.1 Internal Filtering

The GEM is configured to have four internal specific address filters configured. Each filter can be configured to

contain a MAC address, which can be specified to be compared against the source address (SA) or destination

address (DA) of each received frame. There is also a mask field to allow certain bytes of the address to be excluded

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Overview

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