MPFS160T datasheet(35/50 Pages) MICROCHIP

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• 480 MHz operation

• Two-port memory with 64 words of 12 bits

• The write port operates synchronously

• The write port has a fixed width

• The read port operates asynchronously and supports synchronous and pipeline operations with the FPGA fabric

flip-flops

• The Libero SoC Design Suite provides automated combining and cascading for larger memories

• Multiple memory blocks can be combined to extend the depth or width

• Provides a state-keeping, low-power suspend mode

• Implemented as an array of latches

4.4.5

µPROM

The µPROM is a single monolithic non-volatile memory that provides a PROM-like storage for a variety of purposes,

including initialization data for other memories, user calibration data, and so on. The memory cells are constructed

from the FPGA configuration cells and are updated when the device is programmed.

The following are key features of the µPROM:

• 10 ns read access time

• Programmed with the FPGA bitstream

• Asynchronous or synchronous read access mode from the FPGA fabric

4.4.6

sNVM

Each PolarFire SoC FPGA has 56 KB of sNVM. The sNVM is organized into 221 pages of 236 bytes or 252 bytes,

depending on whether the data is stored as plain text or encrypted/authenticated data. It is accessible to users

through system services calls to the PolarFire SoC FPGA system controller. Pages within the sNVM can be marked

as ROM during bitstream programming. The sNVM content can be used to initialize LSRAM and µSRAMs with

secure data. The sNVM is only accessible through system service calls. Data written to the sNVM can be protected

by the PUF. The sNVM can be used to store user secure boot code for the microprocessor subsystem and encryption

keys.

4.4.7

Math Block

The fundamental building block in any digital signal processing algorithm is the multiply-accumulate (MACC)

operation. PolarFire SoC FPGAs implement a custom 18 x 18 MACC block for an efficient, low-power implementation

of complex DSP algorithms such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and

fast Fourier transform (FFT) for filtering and image processing applications. An optional 16-word coefficient ROM can

be constructed from logic elements located near the math block.

The following are key features of the math block functionality:

• 500 MHz operation

• 18 × 18 two's complement multiplier accumulator with an output width of 48 bits

• Power-saving pre-adder to optimize linear phase FIR filter applications and reduce the math block usage

• Optional pipelining and dedicated buses for cascading

• Dot-product mode for complex multiplies

The following illustration shows the functional blocks of the math block.

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 35

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