Table 3-2. U54 Application Cores

Feature

Description

ISA

RV64IMAFDC (RV64GC)

Instruction cache

32 KB, 8-way

Instruction tightly

integrated memory (ITIM)

Maximum of 28 KB

Data cache

32 KB, 8-way

ECC support

Single-error correct, double-error detect on the instruction cache/ITIM and data cache

Virtual memory support

The U54 has support for Sv39 virtual memory support with a 39-bit virtual address

space, 38-bit physical address space, and 32-entry TLB

Privileged modes

Machine (M), Supervisor (S), User (U)

3.1.2.1

U54 Instruction Memory System

The instruction memory system consists of a dedicated 32 KB, 8-way, set-associative, Virtually Indexed Physically

Tagged (VIPT) instruction cache. The access latency of all blocks in the instruction memory system is one clock

cycle. The instruction cache is not kept coherent with the rest of the platform memory system. Writes to instruction

memory must be synchronized with the instruction fetch stream by executing a FENCE.I instruction. The instruction

cache has a line size of 64 bytes and a cache line fill will trigger a burst access outside of the PolarFire SoC CPU

core complex. The core will cache instructions from executable addresses, with the exception of the ITIM. Trying to

execute an instruction from a non-executable address will result in a synchronous trap.

3.1.2.2

U54 I-Cache Reconfiguration

The instruction cache can be partially reconfigured into an Instruction Tightly Integrated Memory (ITIM), which

occupies a fixed address range in the memory map. ITIM provides high-performance, predictable instruction delivery.

Fetching an instruction from ITIM is as fast as an instruction-cache hit, with no possibility of a cache miss. ITIM

can hold data as well as instructions, though loads and stores to ITIM are not as performant as loads and stores to

DTIM. The instruction cache can be configured as ITIM for all ways except for 1 in units of cache lines (64 bytes).

A single-instruction cache way must remain as an instruction cache. ITIM is allocated simply by storing to it. A store

to the nth byte of the ITIM memory map reallocates the first n+1 bytes of instruction cache as ITIM, rounded up to

the next cache line. ITIM is deallocated by storing zero to the first byte after the ITIM region. The deallocated ITIM

space is automatically returned to the instruction cache. For determinism, software must clear the contents of ITIM

after allocating it. It is unpredictable whether ITIM contents are preserved between deallocation and allocation.

3.1.2.3

U54 Instruction Fetch Unit

The U54 instruction fetch unit contains branch prediction hardware to improve performance of the processor core.

The branch predictor comprises a 40-entry branch target buffer (BTB) that predicts the target of taken branches, a

128-entry branch history table (BHT) that predicts the direction of conditional branches, and a 2-entry return-address

stack (RAS) that predicts the target of procedure returns. The branch predictor has a one-cycle latency, so that

correctly predicted control-flow instructions result in no penalty. Mispredicted control-flow instructions incur a three-

cycle penalty. The branch predictor can be turned off during device configuration to create deterministic systems. The

U54 implements the standard Compressed (C) extension to the RISC-V architecture which allows for 16-bit RISC-V

instructions.

3.1.2.4

U54 Execution Pipeline

The U54 execution unit is a single-issue, in-order pipeline. The pipeline comprises five stages: instruction fetch,

instruction decode and register fetch, execute, data memory access, and register writeback.

The pipeline has a peak execution rate of one instruction per clock cycle, and is fully bypassed so that most

instructions have a one-cycle result latency. There are several exceptions:

• LW has a two-cycle result latency, assuming a cache hit.

• LH, LHU, LB, and LBU have a three-cycle result latency, assuming a cache hit.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 12