...........continued

Interface

Direction

I/O Data

Rate

I/O Clock Rate

(MHz)

Gear

Ratio

FPGA Clock Rate

(MHz)

Applications

MIPI-DPHY

Input/

Output

800 Mbps/

500 Mbps

250

2:1

125

MIPI CSI, DSI

Wide LVDS

Input/

Output

1.6 Gbps

800

8, 4,

2:1

250

ADC, DAC

4.4

Non-Volatile FPGA Fabric

The non-volatile FPGA fabric is built on state-of-the-art 28nm low power non-volatile process technology. The

PolarFire SoC FPGA fabric is composed of the following building blocks:

• Logic element

• On-chip memory (LSRAM, μSRAM, sNVM, and μPROM)

• Math block

The FPGA fabric configuration cells are SEU immune, and are used to configure I/Os and other aspects of the

device. Non-volatile FPGAs do not require the configuration process inherent in SRAM FPGAs. Non-volatile FPGAs

power up quickly like an ASIC with minimal inrush current, and are ideal for root-of-trust, first-up functionality in any

system.

4.4.1

Logic Element

The 4-input LUT can be configured either to implement any 4-input combinatorial function or to implement an

arithmetic function where the LUT output is XORed with a carry input to generate the sum output.

The logic element has the following features.

• A fully permutable 4-input LUT optimized for lowest power

• A dedicated carry chain based on a carry look-ahead technique

• A separate flip-flop that can be used independently from the LUT

4.4.2

On-Chip Memory

PolarFire SoC FPGAs integrate four different types of memories that allow the designer to optimize for power,

functionality, and area. Two memory types are volatile, and two memory types are non-volatile.

Volatile memories:

• LSRAM

• µSRAM

The LSRAMs are 20 Kb SRAMs with a built-in SECDED and interleaving to prevent multi-bit upsets (MBUs). The

µSRAMs are small distributed 64 x 12 RAMs, well suited for efficient implementation of small buffers, thereby

reserving LSRAM usage for the wider and deeper memories.

Non-volatile memories (NVMs):

• µPROM

• sNVM

The µPROM, constructed of SEU-immune, FPGA-configuration non-volatile cells, is readable at run time and writable

during device programming. It provides users with SEU-immune parameters, constants, IDs, and parametric or

initialization data. The sNVM is accessible through system service calls. Data written to the sNVM can be protected

by the PUF. The sNVM is readable and writable by the designer’s application during runtime and is an ideal storage

location for user keys and user secure boot code for the microprocessor subsystem.

4.4.3

LSRAM

Each LSRAM block consists of 20,480 bits of RAM and includes functionality to support dual-port and two-port

modes. There are numerous configurations and features for each block. The Libero SoC Design Suite has an

Programmable Logic Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 33