MPFS160T datasheet(41/50 Pages) MICROCHIP

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Reliability

Microchip continues to offer the industry’s most reliable FPGAs for your mission and safety critical applications.

7.1

FPGA Fabric

PolarFire SoC FPGA configuration cells are inherently immune to SEUs caused by neutrons. Contrary to popular

belief, shielding does not prevent a neutron from passing through an electronic system or electronic device. As

semiconductor device geometry shrinks to smaller lithography, the problem of MBUs starts appearing. SRAM FPGA

scrubbing techniques might be inadequate in these circumstances and while scrubbing may help, an important point

is that scrubbing detects an error after the fact. The error has already occurred and propagated throughout the

system. The configuration of the PolarFire SoC FPGA fabric provides worry-free operation against random events

caused by SEUs.

7.2

LSRAM

LSRAMs have built-in SECDED capability on a 32-bit word boundary. Seven additional bits are used for error

correction. Two flags are provided to the user to indicate SECDED. Mitigation against multi-bit upsets is provided

by keeping all cells in a word separated by a minimum distance. Applications that require scrubbing need to be

accomplished with user logic. The error correction logic can be turned ON and OFF by the user to enable easy

validation of the error correction operation.

7.3

µSRAM

The 64 × 12 µSRAMs are constructed from latches and are not as sensitive to SEUs as SRAMs are.

7.4

Digests

Digests verify the integrity of the programmed non-volatile data. Digests are a cryptographic hash of various data

areas. Any digest that reports back an error raises the digest tamper flag.

The following are digestible non-volatile areas:

• The FPGA fabric and consequently the µPROM

• sNVM marked as ROM

• User key 1

• User key 2

• Factory parametric and key storage

• 128 KB eNVM block

7.5

System Controller Suspend Mode

For safety critical applications, PolarFire SoC FPGAs allow the user to place the Cortex-M3-based system controller

in a reset state after the FPGA has powered up. By programming an SEU configuration non-volatile bit, the system

controller is placed in reset by a TMRed SEU immune reset latch after FPGA power-up. User logic can monitor if

the suspend mode command is active and if the system controller cannot fetch instructions while in the reset state.

The FPGA can be re-programmed after disabling the suspend mode by asserting the appropriate JTAG signals. The

JTAG TRSTB signal must be asserted low for suspend mode to remain active.

The following illustration shows how to activate and deactivate suspend mode.

Reliability

and its subsidiaries

Overview

DS60001656C-page 41

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