data clock available to the fabric, and can be used directly to register the parallel data coming from the internal

logic. The transmit parallel data has additional hardware support for the 8b/10b, 64b/66b, or 64b/67b encoding

schemes to provide a sufficient number of transitions. The bit-serial output signal drives two package pins with

differential signals. The output signal pair supports a wide variety of serial protocols and has programmable signal

swing, as well as programmable pre- and post-emphasis to compensate for PC board losses and other interconnect

characteristics. For shorter channels, the swing can be reduced to lower power consumption. Each transmit lane can

be sourced by one of two transmit PLLs. Each transmit PLL can drive up to four transceiver lanes. Transmitter PLLs

are state-of-the-art fractional frequency synthesizers with integrated jitter attenuation.

4.3.1.3

Receiver

The receiver is fundamentally a serial-to-parallel converter with clock recovery changing the incoming bit-serial

differential signal into a parallel stream of words of 8, 10, 16, 20, 32, 40, 64, or 80 bits. This allows the FPGA

designer to trade off the internal data path width versus logic timing margin. The receiver takes the incoming

differential data stream, feeds it through programmable linear and decision feedback equalizers (to compensate for

PC board and other interconnect characteristics), and uses the reference clock input to initiate clock recognition. The

data pattern uses non-return-to-zero (NRZ) encoding and optionally guarantees sufficient data transitions by using

the selected encoding scheme. The outgoing parallel data has additional hardware support for the 8b/10b, 64b/66b,

or 64b/67b encoding schemes to provide a sufficient number of transitions. Parallel data is transferred into the FPGA

logic using the recovered clock (RX_CLK).

4.3.1.4

Transceiver Lane Modes

The transceiver lane supports the following five modes of operation.

• PMA—direct access to the PMA without any encoding

• 8b/10b—8b/10b encoding/decoding is provided

• 64b/6xb—64b/66b or 64/67b encoding/decoding with gearbox logic is provided

• PIPE—a PIPE interface supporting both PCIe Gen2 and SATA 3.0

• PCIe—direct connection to the embedded PCIe Gen2 controller

The following illustration shows the collaboration of the five modes that the transceiver lanes support.

Programmable Logic Subsystem

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Overview

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