Figure 3-1. Interrupts

For more information on interrupts, see the PolarFire SoC MSS Technical Reference Manual.

3.4

Memory Subsystems

PolarFire SoC contains an on-chip 128 KB embedded non-volatile memory (eNVM) for user code, a flexible L2

memory subsystem, and an integrated DDR memory controller.

3.4.1

L2 Memory Subsystem

The PolarFire SoC Level 2 Cache Controller is used to provide access to fast copies of memory for masters in a

core complex. The Level 2 Cache Controller also acts as a directory-based coherency manager. The Level 2 Cache

Controller offers extensive flexibility as it allows for several features in addition to the Level 2 Cache functionality,

such as memory-mapped access to L2 Cache RAM for disabled cache ways, scratchpad functionality, way masking

and locking, and ECC support with error tracking statistics, error injection, and interrupt signaling capabilities.

The L2 Cache Controller consists of 4 banks where each bank contains 512 sets of 16 ways, and each way contains

a 64-byte block. This subdivision into banks helps facilitate increased available bandwidth between CPU masters and

the L2 Cache, as each bank has its own 128-bit inner port. As such, multiple requests to different banks may proceed

in parallel. The outer port of the L2 Cache Controller is a 128-bit port shared among all banks and is connected to the

DDR controller.

When cache ways are disabled, they are addressable in the L2 Loosely Integrated Memory (L2LIM) address space

as described in the PolarFire SoC MSS Technical Reference Manual. Fetching instructions or data from the L2-LIM

provides deterministic behavior equivalent to an L2 cache hit, with no possibility of a cache miss. Accesses to L2-LIM

are always given priority over cache way accesses which target the same L2 cache bank. Out of reset all ways,

except for way 0, are disabled. Cache ways can be enabled by writing to specific control registers. Once a cache way

is enabled, it can not be disabled unless the CPU complex is reset. The highest numbered L2 cache way is mapped

to the lowest L2-LIM address space, and way 1 occupying the highest L2-LIM address range. As L2 cache ways are

enabled, the size of the L2-LIM address space shrinks.

The L2 Cache Controller has a dedicated scratchpad address region that allows for allocation into the cache using

an address range which is not memory backed. This address region is denoted as the L2 Zero Device in the memory

map. Writes to the scratchpad region will allocate into cache ways that are enabled and not masked. Care must

be taken with the scratchpad, however, as there is no memory backing this address space. Cache evictions from

addresses in the scratchpad will result in data loss. The main advantage of the L2 Scratchpad over the L2-LIM is

Microprocessor Subsystem

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and its subsidiaries

Overview

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