3.1.2.10.2 U54 Memory Error Reporting

ECC events are reported by the Bus-Error Unit (BEU) for a given core. The BEU can be configured to generate

interrupts either globally to the Platform Level Interrupt Controller (PLIC), or locally to the specific part where the ECC

event occurred. When BEU interrupts are enabled, software can then be used to monitor and count ECC events.

In order to detect uncorrectable ECC errors in the L1 memory system, interrupts must be enabled in the BEU.

Specifically, to halt execution of a core when an uncorrectable instruction is detected, the BEU must be configured

to generate a local interrupt. Uncorrectable ECC errors in the L1 system are also reported to the FPGA fabric as a

HALT_CPU_n signal, where n = 0 –5 and n = 1 through 5 = the U54 application cores.

3.1.3

Physical Memory Protection

Each CPU in PolarFire SoC includes a physical memory protection (PMP) unit compliant with the RISC-V Instruction

Set Manual, Volume II: Privileged Architecture, Version 1.10. The PMP unit can be used to set memory access

privileges (read, write, execute) for specified memory regions. Each PMP supports 16 regions with a minimum region

size of 4 bytes.

3.1.3.1

Functional Description

PolarFire SoC includes a Physical Memory Protection (PMP) unit, which can be used to restrict access to memory

and isolate processes from each other. The PMP unit has 16 regions and a minimum granularity of 4 bytes. It is

permitted to have overlapping regions. The PolarFire SoC PMP unit implements the architecturally defined pmpcfgX

CSRs pmpcfg0 and pmpcfg2 supporting 16 regions. pmpcg1 and pmpcfg3 are implemented but hardwired to zero.

3.1.3.2

Region Locking

The PMP allows for region locking whereby once a region is locked, further writes to the configuration and address

registers are ignored. Locked PMP entries may only be unlocked with a system reset. A region may be locked by

setting the L bit in the pmpicfg register. In addition to locking the PMP entry, the L bit indicates whether the R/W/X

permissions are enforced on M-Mode accesses. When the L bit is set, these permissions are enforced for all privilege

modes. When L bit is clear, the R/W/X restrictions apply only to U-mode.

3.2

Debug

3.2.1

CPU Debug

Each CPU has up to ten breakpoint registers. Breakpoints can halt the respective CPU under the following

conditions.

• Address match on Load

• Address match on Store

• Address match on Instruction Fetch

• Address match on User mode

• Address match on Supervisor mode

• Address match on Machine mode

A successful match on address can generate an exception or place the machine into debug mode.

3.2.2

Trace

PolarFire SoC includes an Instruction trace interface module. For each core, the following can be captured when an

instruction is retired or trapped and trace is enabled.

• The address of the instruction

• The instruction

• Privileged mode during execution

• Trap or retired indication

• Interrupt or exception indication

• Exception cause

• Exception data

Microprocessor Subsystem

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and its subsidiaries

Overview

DS60001656C-page 14