MPFS160T datasheet(21/50 Pages) MICROCHIP

21 / 50 page

• Hardware-selectable option for 8-bit/4-bit LPI interface

• Vendor control and status register enabled with width of 4 and 8, respectively

• Number of DMA channels: 4

• Dynamic FIFO support allows dynamic allocation of buffer depth per enabled endpoint

3.5.4

User Crypto

PolarFire SoC embeds an Athena TeraFire F5200B side channel resistant crypto coprocessor and is available on

"S" data security devices. For the list of devices that support data security, see Table 9-1. PolarFire SoC Offerings.

The user crypto core can be mapped between the MSS and the FPGA fabric via a hardware based handshaking

mechanism. The crypto core also supports the F5200B streaming interface directly into the fabric. Internal memories

in the Athena core are SECDED protected.

3.5.4.1

TeraFire EXP-F5200B Supported Protocols Features

• TRNG SP800-90A CTR_DRBG-2565; SP800-90B (draft) NRBG

• AES 128/192/256 key lengths E/D (ECB, CBC, CTR, OFB, CFB, GCM, KeyWrap)

• SHA-1/224/256/384/512

• HMAC-SHA-1/224/256/384/512; GMAC-AES; CMAC-AES

• SHA-256 Key Tree

• ECC: NIST P256/384/521 and Brainpool P256/384/512 curves; KeyGen, KAS - ECC CDH, ECDSA SigGen &

SigVer, PKG, PKV

• IFC: 1024/1536/2048/3072/4096 RSA E/D; SSA_PKCS1_V1_5 SigGen & SigVer; ANSI X9.31 SigGen & SigVer

• FFC: 1024/153/2048/3072/4096; KAS - DH, DSA SigGen & SigVer

3.5.5

Controller Area Network

PolarFire SoC integrates two controller area network cores compliant to CAN 2.0 A and B and conforms to ISO

11898-1. Internal message SRAM is SECDED-protected. The following are CAN controller features.

3.5.5.1

Receive Path

• 32 receive buffers

• Each buffer has its own message filter

• Message filter covers: ID, IDE, RTR, data byte 1, and data byte 2

• Message buffers can be linked together to build a bigger message array

• Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt

3.5.5.2

Transmit Path

• 32 Tx message holding registers with programmable priority arbitration

• Message abort command

• Single-shot transmission (no automatic re-transmission upon error or arbitration loss)

3.5.5.3

Debugging Support

• Listen only mode

• Internal loop back mode

• External loop back mode

• Error capture register

• SRAM test mode to support software based memory testing (SRAM is addressable by the CPUs if the core is

disabled)

3.5.6

QSPI XIP Controller

PolarFire SoC integrates a Quad SPI (QSPI) flash controller with eXecute In Place (XIP) capabilities. The following

are QSPI features.

• Master SPI Data Rate

Microprocessor Subsystem

and its subsidiaries

Overview

DS60001656C-page 21

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