MPFS160T datasheet(2/50 Pages) MICROCHIP

2 / 50 page

– Boot directly from eNVM

• Platform interrupt controller

– 185 interrupt sources from the microprocessor subsystem and FPGA fabric with seven priority levels

• Local interrupt controller

– 48 local interrupts sourced from the FPGA drive the local interrupt controller on each core

• Debug

– Ten hardware triggers per CPU (triggers can be configured as a breakpoint or a watchpoint)

– Instruction trace on all CPUs

– Performance counters

– Runtime-configurable AXI bus monitors

• Monitor AXI commands to DDR

• Monitor an AXI port going into or out of the AMBA I/O AXI switch

– 32-bit fabric monitor

– SmartDebug

• Dynamically monitor any two nets in the FPGA on two pins without changing the FPGA design

• Read/write to FPGA flip-flops and memories

• Halt clock trees, inspect logic tree

• FPGA breakpoints

• SmartDebug integrated into processor debug transport layer—debug from a single tool chain

– Secure debug remotely over Ethernet (both the processor subsystem and the FPGA design)

• Processor I/O

– Two GigE MACs

– One USB 2.0 OTG

– MMC 5.1 SD/SDIO

– Two CAN 2.0 A and B

– Execute in place Quad SPI flash controller

– Five multi-mode UARTs

– Two SPI, two I2C

– RTC, GPIO

– Five watchdog timers

– Timers

• Processor to FPGA Interconnect

– Two 64-bit processor-fabric bidirectional AXI4 interfaces

– One 64-bit fabric-to-processor AXI4 interface

– One 32-bit processor-to-fabric APB interface

FPGA Features

• Up to 461k logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flip-flop

• 20 Kb dual- or two-port large static random access memory (LSRAM) block with built-in SECDED

• 64 × 12 two-port µRAM block implemented as an array of latches

• 18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16-deep × 18 coefficient ROM

• Built-in µPROM, modifiable at program time and readable at run time for user data storage

• High-speed serial connectivity with built-in, multi-gigabit, multi-protocol transceivers from 250 Mbps to 12.7 Gbps

• Integrated dual x4 PCIe Gen2 endpoint (EP) and root port (RP) designs

• High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps LPDDR3/DDR3

memories with integrated I/O digital

• General-purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps DDR3, and

1250 Mbps LVDS I/O speed with integrated I/O digital logic

• Low-power, phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low jitter

and its subsidiaries

Overview

DS60001656C-page 2

MPFS160T 数据表(PDF) 2 Page - Microchip Technology

MPFS160T 数据表(HTML) 2 Page - Microchip Technology

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