Table 3-5. Processor-to-Fabric Interconnect

Interface

Type

Width

MSS to Fabric

Fabric to MSS

DLL

FIC_0

AXI4

64b

Yes

Yes

Yes

FIC_1

AXI4

64b

Yes

Yes

Yes

FIC_2

AXI4

64b

No

Yes

Yes

FIC_3

APB

32b

Yes

No

Yes

3.7

Secure Boot

PolarFire SoC comes with two secure boot options. For the default PolarFire SoC secure boot method, the system

controller will copy the Microchip secure boot loader from its private, secure memory area and load it into the 8 KB

DTIM of the E51 monitor core. Reset will be released to the CPUs and the boot code will start executing. The default

secure boot loader will perform a signature check on the 128 KB eNVM then run a hash on the eNVM image. If no

errors are reported, the code will jump to the eNVM. If errors are reported, the system controller will activate a tamper

alarm that asserts a signal to the FPGA fabric. Users can then decide on a plan of action.

The second secure boot method allows users to place their own boot code in the secure non-volatile memory

(sNVM) area of the chip. The sNVM is a 56 KB nonvolatile memory that can be protected by the built-in Physically

Unclonable Function (PUF), meaning the unique PUF ID can serve as an initialization vector for an AES encrypt/

decrypt operation performed by the side-channel resistant system controller co-processor. On power-up, the system

controller will decrypt and copy the user code from sNVM and write it to the E51 monitor core DTIM. From there, your

custom secure boot loader starts executing.

3.8

Peripheral Memory SECDED Reporting and Error Injection

The Gigabit Ethernet MACs, the MMC 5.1 controller, the USB OTG controller, the CAN controllers, the crypto

core and memory in the built-in MSS DDR controller are protected with by single-error correct, double-error detect

(SECDED) error correction code (ECC) subsystem, which adds 7 bits to 32-bit memories and 8 bits to 64-bit

memories. The memories within the CPU system have their own ECC control and reporting systems. The external

DDR memory supports optional ECC (using a fifth DDR bank). Each MSS internal memory system has its own set

of control and status registers, which consists of a status, interrupt enable, count, and error injection registers. When

a two-bit error is detected, the data will not be corrected. If the data is being read over an internal AMBA bus, the

system will respond with an APB, AHB, or AXI error response marking the data as corrupted. If the interrupt is

enabled, an interrupt will also be generated. If the data is not being read over an AMBA bus like USB, CAN, Ethernet

transmit data then corrupted data will be transmitted, and an interrupt generated. The system can then respond to

the bus error event or interrupt and take the appropriate recovery action. ECC error injection is supported to ease

customer validation of the error correcting subsystem. Data may be written with 1-, 2-, or 3-bit errors by setting the

appropriate EDAC error injection control registers.

3.9

DMA Controller

The PolarFire SoC MSS Direct Memory Access (DMA) controller supports up to 4 channels of independent

simultaneous transfers. Each channel has its own set of control registers and two interrupts, complete and error.

Bus transaction sizes are programmable and the transactions can be auto-loaded into the DMA engine. The DMA

engine works in conjunction with hart software services (firmware running on the E51).

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 24