LSRAM configurator that provides automated combining and cascading of several LSRAM blocks into larger

memories.

LSRAM features include:

• 428 MHz operation

• True dual-port memory

• Two-port memory (one dedicated write port, one dedicated read port)

• Data widths of ×1, ×2, ×5, ×10, ×20, ×40, and ×33 with SECDED enabled

• Multi-bit-upset mitigation

• Synchronous operation

• Independent port clocks

• Byte enables

• Registered inputs

• Output registers with separate enables and synchronous resets

• Read enables to conserve power while retaining output data

• Power switch to minimize static power when the LSRAM is not used

• Fast zeroization mode

4.4.3.1

Dual-Port Mode

In dual-port mode, the width of both ports is less than 33 and the ports are independent of each other. The write and

read operations can occur independently of each other, at any location. On write collisions, while the write operations

occur correctly, the read operations can return ambiguous results while the write completes. After completing the

write operation, the read data reads the newly written write data correctly.

4.4.3.2

Two-Port Mode

In two-port mode, at least one port has a width of 32 or 40 (or 33 with SECDED). Port A is dedicated for reads and

port B is dedicated for writes.

The following illustration shows port widths in various modes.

Figure 4-5. LSRAM Dual- and Two-Port Configurations

4.4.4

µSRAM

The µSRAM is a two-port memory embedded in the FPGA fabric, which is provided for an efficient low-power

implementation for small buffers. On write collisions, the write operations occur correctly, while the read operations

can return ambiguous results while the write completes. After completing the write operation, the read data reads the

newly written write data.

The following are key features of the µSRAM block:

Programmable Logic Subsystem

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Overview

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