MPFS160T datasheet(36/50 Pages) MICROCHIP

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4.5

PCI Express

Each PolarFire SoC FPGA integrates two low-power, built-in PCIe Gen2 controllers, allowing seamless and easy

connectivity to one or more host processors. The two PCIe controllers are shared across two quads. For more detail,

see UG0920: PolarFire SoC FPGA PCI Express User Guide.

4.5.1

PCI Express Features

The following are PCIe features.

• ×1, ×2, and ×4 lane support

• Suitable for root port, native endpoint

• PCI Express base specification revision 2.0 and 1.1 compliant

• AXI4 master and slave interfaces to the FPGA fabric

• Single function capability

• Advanced error reporting (AER) support

• Integrated clock domain crossing (CDC) to support user-selected AXI4 frequency

• Lane reversal support

• Legacy PCI power management support

• Native active state power management L0s and L1 state support

• Power management event (PME message)

• MSI and legacy INT message support

• Latency tolerance reporting (LTR)

• L1 PM sub-states with CLKREQ

• Address translation tables between the PCIe and AXI4 domains

4.5.2

PCI Express DMA Engines

Each PCIe controller supports the following built-in DMA modes, enabling low-power and efficient data transfer into

the FPGA fabric.

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 36

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