3.1.1.4

E51 Execution Pipeline

The E51 execution unit is a single-issue, in-order pipeline. The pipeline comprises five stages: instruction fetch,

instruction decode and register fetch, execute, data memory access, and register writeback. The pipeline has a peak

execution rate of one instruction per clock cycle. It is fully bypassed, so that most instructions have an apparent

one-cycle result latency. There are several exceptions:

• LD and LW have a two-cycle result latency, assuming a cache hit.

• LH, LHU, LB, and LBU have a three-cycle result latency, assuming a cache hit.

• MUL, MULW, MULH, MULHU, MULHSU, DIV, DIVU, REM, REMU, DIVW, DIVUW, REMW, and REMUW have

between a 2-cycle and 66-cycle result latency, depending on operand values.

• CSR reads have a three-cycle result latency.

The pipeline only interlocks on read-after-write and write-after-write hazards, so instructions may be scheduled to

avoid stalls.

The iterative multiplier is configured to produce 16 bits per cycle with an early-out option. The iterative divider has

latency of between three and 66 cycles and an early-out option.

Branch and jump instructions transfer control from the memory access pipeline stage. Correctly predicted branches

and jumps incur no penalty, whereas mispredicted branches and jumps incur a three-cycle penalty. Most CSR writes

result in a pipeline flush, a five-cycle penalty.

3.1.1.5

E51 Data Memory System

The E51 data memory system consists of 8 KB Data Tightly-Integrated Memory (DTIM). The access latency is two

clock cycles for full words and three clock cycles for smaller quantities. Misaligned accesses are not supported in

hardware and result in a trap to support software emulation. Stores are pipelined and commit on cycles where the

data memory system is otherwise idle. Loads to addresses currently in the store pipeline result in a five-cycle penalty.

3.1.1.6

E51 Memory Error Correction

The E51 DTIM implements single-error correcting, double-error detecting (SECDEC) error correcting code (ECC).

The granularity at which this protection is applied (the codeword) is 32 bits (with an ECC overhead of 7 bits per

codeword).

3.1.1.6.1 E51 Memory Single-Bit Errors

When a single bit error is detected in the E51 L1 memory used as a cache, the error is corrected and the cache

line is flushed consequently writing to the next level in the memory hierarchy (L2 cache). When a single bit error is

detected in the the E51 L1 memory configured as an ITIM, the error is corrected and written back to the ITIM location.

3.1.1.6.2 E51 Memory Error Reporting

ECC events are reported by the Bus-Error Unit (BEU) for a given core. The BEU can be configured to generate

interrupts either globally to the Platform Level Interrupt Controller (PLIC), or locally to the specific part where the ECC

event occurred. When BEU interrupts are enabled, software can then be used to monitor and count ECC events.

In order to detect uncorrectable ECC errors in the L1 memory system, interrupts must be enabled in the BEU.

Specifically, to halt execution of a core when an uncorrectable instruction is detected, the BEU must be configured

to generate a local interrupt. Uncorrectable ECC errors in the L1 system are also reported to the FPGA fabric as a

HALT_CPU_n signal, where n indicates the core (0= E51 core).

3.1.1.7

E51 Local Interrupts

The E51 supports up to 48 local interrupt sources routed directly to the core. The local interrupts are sourced from

the FPGA fabric. The E51 core receives the same 48 interrupt sources from the FPGA fabric as do the U54 cores.

3.1.2

U54 Application Cores

The U54 application core is 64-bit embedded RISC-V microprocessor, including an instruction fetch unit, an execution

pipeline, and a data memory system. The application core supports the standard RISC-V RV64IMAFDC (RV64GC)

user-level instruction set, with machine, supervisor, and user privilege modes.The U54s may run a rich operating

system such as Linux, an RTOS or a bare metal application.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 11