MPFS160T datasheet(22/50 Pages) MICROCHIP

22 / 50 page

– Programmable SPI clock HCLK/2, HCLK/4 or HCLK/6

– Maximum data rate is HCLK/2

• FIFOs

– Transmit and Receive FIFO

– 16-byte transmit FIFO depth

– 32-byte receive FIFO depth

• SPI Protocol

– Master operation

– Motorola SPI supported

– Slave select operation in idle cycles configurable

– Supports extended SPI operation (1, 2, and 4 bits)

– Supports QSPI operation (4-bit operation)

– Supports BSPI operation (2-bit operation)

– Support XIP (execute in place)

– Supports 3 or 4-byte SPI address.

• Frame Size

– Supports 8-bit frames directly

– Back-to-back frame operation supports >8-bit frames

– Supports up to 4GB Transfer (2**32 bytes)

• Processor Overhead Reduction

– Support of SPI flash command/data packets with automatic data generation and discard function

3.5.7

Serial Peripheral Interface

Serial peripheral interface (SPI) is a synchronous serial data protocol that enables the microprocessor or

microcontroller and peripheral devices to communicate with each other. The SPI controller provides a serial interface

compliant with the Motorola SPI, Texas Instruments synchronous serial, and National Semiconductor MICROWIRE™

formats. In addition, SPI supports interfacing with large SPI flash and EEPROM devices and a hardware-based slave

protocol engine. There are two identical SPI controllers in the MSS.

• The SPI peripherals support the following features.

• Master and Slave modes

• Selectable slaves (up to 8)

• Configurable slave select operation

• Configurable clock polarity

• Separate transmit (Tx) and receive (Rx) FIFOs to reduce interrupt service loading

3.5.8

Multi-Mode UART

The PolarFire SoC multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) performs serial-

to parallel conversion on data originating from modems or other serial devices, and performs parallel-to serial

conversion on data from the CPUs. PolarFire SOC contains 5 identical MMUARTs. The MMUART is software

compatible with the popular 16550 UART device.

The MMUART peripherals support the following features.

• Asynchronous and synchronous operations

• Full programmable serial interface characteristics

• Data width is programmable to 5, 6, 7, or 8 bits

• Even, odd, or no-parity bit generation/detection

• 1, 1½, and 2 stop bit generation

• 9-bit address flag capability used for multi-drop addressing topologies

• Separate transmit (Tx) and receive (Rx) FIFOs to reduce processor interrupt service loading

Microprocessor Subsystem

and its subsidiaries

Overview

DS60001656C-page 22

MPFS160T 数据表(PDF) 22 Page - Microchip Technology

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