MPFS160T datasheet(32/50 Pages) MICROCHIP

32 / 50 page

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VDDIO (V)

LVCMOS18

LVCMOS15

LVCMOS12

1.2

Not available

Yes

4.3.3

I/O Digital

The PolarFire SoC FPGA I/O digital logic is used to interface between the FPGA fabric and the I/O buffers. It

interfaces between the high-speed I/O buffers and lower-speed FPGA fabric. The I/O digital block consists of the

following:

• Delay chain for input or output delay

• Registers and control logic for input modes and output modes

The I/O digital registers can be configured for both input and output DDR and shift register modes and combined

DDR-shift register modes. It allows gearing up the output data rate and gearing down the input data rate. The

PolarFire SoC FPGA I/O digital logic works in conjunction with fast and low-skew clock distributions optimized for

DDR applications, special clock dividers, and other support circuits to guarantee clock domain crossings.

4.3.3.1

I/O Digital Features

The following are I/O digital features.

• Programmable input and/or output delay chain

• Data eye monitor for detecting margin-to-clock edges

• Data eye position optimizer

• Up to 10:1 input deserialization

• Up to 10:1 output serialization

• Support for DDR and SDR interfaces

• Receive slip control to facilitate word alignment

• Fast and low-skew lane clocks per 12 I/Os

• Clock recovery for SGMII and similar interfaces (one per 12 I/Os)

• Flash*Freeze support

4.3.3.2

I/O Digital Modes

The following table lists the associated memory interface, I/O data rate, FPGA clock rate, and its applications.

Table 4-4. I/O Digital Modes

Interface

Direction

I/O Data

Rate

I/O Clock Rate

(MHz)

Gear

Ratio

FPGA Clock Rate

(MHz)

Applications

DDR4

BiDir

1.6 Gbps

800

8:1

200

Memory interface

DDR3 (L)

BiDir

1.3 Gbps

650

8:1

162.5

Memory interface

LPDDR3

BiDir

1.3 Gbps

650

8:1

162.5

Low-power memory

interface

QDRII+

Input/

Output

1.1 Gbps

550

8:1

137.5

Low-latency memory

interface

RLDRAM3

Input/

Output

1.0 Gbps

500

8:1

125

Low-latency memory

interface

7:1 LVDS

Input

800 Mbps

400

7:1

114

Flatlink, Cameralink

CDR

Input

1.25 Gbps

625

10:1

125

1000BASE-T, SGMII

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 32

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