ADP5140WACCZ-R7 datasheet(37/128 Pages) AD

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Data Sheet

ADP5140

Rev. 0 | Page 37 of 128

AVIN AND AVDD

The ADP5140 integrates an input UVLO circuit on the input

supply. When VAVIN or VAVDD drops below 2.4 V (typical), an

input UVLO event is detected, and the device turns off. When the

input voltage recovers from the UVLO event, and the input

voltage exceeds 2.5 V (typical), the device is active, and a power-

on reset (POR) signal generates.

ENABLE FUNCTION

The ADP5140 has an enable pin (EN) to control turning the

device on or off. The EN pin has two voltage thresholds, the first

stage threshold (VEN_RGH) and the second stage threshold (VEN_R).

When the voltage on the EN pin (VEN) is below VEN_RGH, the

device is in shutdown mode.

When VEN is between VEN_RGH and VEN_R, the device can enter

initial mode (see the Initial Mode section for more details).

When VEN is above VEN_R, the device exits initial mode and can

operate in normal mode (see the Normal Mode section for

more details).

An internal pull-down resistor prevents the device from

enabling accidentally if the EN pin is left floating.

ACTIVE OUTPUT DISCHARGE

Except for BUCK2 and LDO1, all other buck regulators, LDO

regulators, and the boost regulator on the ADP5140 integrate the

output discharge function. The discharge function is enabled

when a regulator is disabled, which helps discharge the output

capacitor quickly.

SYNCHRONIZATION

The SYNC pin can be configured as an input, output, or high

impendence pin through the SPI. The default configuration is

as a high impedance pin. When the SYNC pin is configured as

an output, the pin outputs a clock that is in phase with BUCK1.

If the SYNC_DIV bit in the FREQ_CONFG register is set to 0,

the frequency on the SYNC pin is equal to the fSW of BUCK1. If

the SYNC_DIV bit is set to 1, the frequency on the SYNC pin is

equal to 1/5 of the BUCK1 fSW.

When the SYNC pin is configured as an input, connect an external

clock ranging from 1.9 MHz to 2.4 MHz to the SYNC pin. The

fSW of the buck regulators and boost regulator is synchronized

to the external clock applied to the SYNC pin. The fSW of BUCK1

runs in phase with the clock on the SYNC pin. The fSW of all

regulators on the ADP5140 clamp at 1.8 MHz if the external

clock frequency is too slow and at 2.5 MHz if the external clock

frequency is too fast.

When the SYNC pin is configured as an input, the frequency

spread spectrum function inside the ADP5140 is disabled.

FREQUENCY SPREAD SPECTRUM

The ADP5140 integrates a triangular frequency spread

architecture to reduce system EMI, as shown in Figure 80. The

frequency spread spectrum function can be enabled or disabled

through the SP_EN bit in the FREQ_CONFG register. The

SP_EN bit is disabled by default. The sweep frequency (fSF) and

sweep depth (SD) can be programmed through the SPI register,

FREQ_CONFG, as shown in Table 19 and Table 20.

fSF

fSW

fSW × (1 + SD)

fSW × (1 – SD)

Figure 80. Triangular Spreading

Table 19. Sweep Frequency Option

SF, Bits[5:3]

Sweep Frequency (kHz)

000 (Default)

001

10.42

010

15.63

011

20.83

100

101

31.25

110

41.67

111

62.5

Table 20. Sweep Depth Option

SD, Bits[8:6]

Sweep Depth (%)

000 (Default)

001

010

011

100

FEEDBACK VOLTAGE MONITOR

Each power rail has a window comparator to monitor the

voltage on the FBx pin. The reference of the FBx window

comparator is derived from an independent band gap and is

window thresholds: warning and fault. If the output voltage is

outside of the warning window or the fault window, a warning

or fault event is triggered accordingly, as shown in Figure 81.

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