ADP5140WACCZ-R7 datasheet(41/128 Pages) AD

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Data Sheet

ADP5140

Rev. 0 | Page 41 of 128

VWDIx

TIME

WINDOW

OPEN

WINDOW

OPEN

WINDOW

tWDx_FAST

tWDx_SLOW

tWDx_FAST

tWDx_SLOW

Figure 85. Both Rising and Falling Edge Signals Trigger WDx

(VWDIx is the Voltage on the WDx Pin)

When the window watchdog is enabled, the watchdog monitors

the trigger edge on the WDIx pin. The window watchdog timer

resets at the trigger edge or when the window watchdog timer

expires if no feeding occurs within the slow window time. The

trigger edge of the WDIx signal must fit into the open window

between the watchdog fast window (tWDx_FAST) and the watchdog

slow window (tWDx_SLOW). If the trigger edge of the WDIx signal

appears outside of the open window, a bad watchdog feed event

occurs, and the watchdog fault counter (the WDTx_FAULT_

COUNTER bits in the WDTx_STATUS register) increments. If

the trigger edge of the WDIx signal appears within the open

window, a good watchdog feed event occurs and the watchdog

fault counter decrements. If the watchdog fault counter value is

equal to or higher than the watchdog fault threshold value (the

WDTx_FAULT_THRESHOLD bits in the WDTx_CTRL

relevant watchdog fail bit in the OTHER_STATUS register and

OTHER_LATCH register.

Window Watchdog Fault Counter

The window watchdog fault counter has overflow saturation

and underflow saturation. When the window watchdog fault

counter is 7, the counter remains at 7 if a bad watchdog feed

event occurs. When the window watchdog fault counter is 0,

the counter remains at 0 if a good watchdog feed event occurs.

The window watchdog fault counter resets when the AVIN

voltage goes below the UVLO threshold or when the watchdog

is re-enabled from the disable status.

Window Watchdog Window Setting

tWDx_FAST and tWDx_SLOW are programmable through the SPI and

the equations to calculate the values are as follows:

tWDx_FAST = WDTx_FAST_WINDOW × Time Tick

tWDx_SLOW = WDTx_SLOW_WINDOW × Time Tick

where:

WDTx_FAST_WINDOW is the value of the

WDTx_FAST_WINDOW bits in the WDTx_WINDOW

WDTx_SLOW_WINDOW is the value of the

WDTx_SLOW_WINDOW bits in the WDTx_WINDOW

Time Tick is determined by the internal 2 MHz clock and the

scale factor, as follows:

Time Tick = SCALE_FACTOR/2 MHz

where:

SCALE_FACTOR depends on the WDTx_PRE_SCALE bits

setting in the WDTx_CTRL register. The default value is 16, as

shown in Table 29.

Table 29. Window Watchdog Scale Factor and Time Tick

WDTx_PRE_SCALE, Bits[1:0]

SCALE_FACTOR

Time Tick (µs)

0.5

01 (Default)

256

128

4096

2048

The default values of tWDx_FAST and tWDx_SLOW are 30 ms and

120 ms, respectively.

The window watchdog needs 2× the time ticks duration time to

reset. Set tWDx_FAST and tWDx_SLOW to no less than 40× the time

ticks to keep the accuracy of the fast window and slow window

at <5%.

Window Watchdog SPI Feeding

Besides using the WDIx signal to feed the window watchdog,

the user can also write an SPI command to the WDTx_SPI_

FEED bits in the WDTx_CTRL register to reset the watchdog

timer. Write 0x51 to the WDT0_SPI_FEED bits to reset the

WD0 timer. Write 0x52 to the WDT1_SPI_FEED bits to reset

the WD1 timer.

WD0 and WD1 are disabled by default and can be enabled

through the SPI. The WDTx_EN_CTRL bit in the WDTx_

CTRL register controls the window watchdogs. Set the WDTx_

EN_CTRL bit to enable the window watchdog and allow the

internal watchdog timer to start counting immediately. Clear

the WDTx_EN_CTRL bit to disable the window watchdog.

Window Watchdog Synchronization

The first feed signal is used for synchronization. As long as the

first feed signal is within the slow window, there is no increment

or decrement on the window watchdog fault counter, and the

watchdog timer resets. If the first feed signal does not come within

the slow window, the watchdog timer expires, the watchdog timer

resets, and the watchdog fault counter increments. The window

watchdog still waits for the first feed signal and treats the first

feed signal as described in this section.

QA Watchdog

The ADP5140 integrates a QA watchdog fed through the SPI.

The QA watchdog can detect software faults of the processor.

The QA_WD_EN_CTRL bit in the QA_WD_CTRL register

controls the QA watchdog. Set the QA_WD_EN_CTRL bit to

enable the QA watchdog, or clear the QA_WD_EN_CTRL bit

to disable the QA watchdog. The default value of the QA_WD_

EN_CTRL bit is 1 (enabled).

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