ADP5140WACCZ-R7 datasheet(52/128 Pages) AD

52 / 128 page

ADP5140

Data Sheet

Rev. 0 | Page 52 of 128

•

Entering peripheral error mode when the peripheral ramp

up times out (tEXP3) or when an overvoltage or

undervoltage event occurs on Regulator 3, Regulator 4,

Regulator 6, Regulator 7, Regulator 8, or Regulator 9.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH occurs.

During peripheral ramp-up mode, Regulator 3, Regulator 4,

Regulator 6, Regulator 7, Regulator 8, and Regulator 9 power

up in a fixed sequence. The FAULT and the STATUS pins keep

low, while the RESET pin is pulled high after a tHOLD delay time.

Normal Mode

A condition for entering normal mode when VAVIN > VAVIN_UVLO_R,

VAVDD > VAVDD_UVLO_R, and VEN > VEN_R is from the peripheral

ramp-up mode when peripheral ramp-up mode completes.

The conditions to exit normal mode include the following:

•

Entering power-down mode when receiving an SPI_CMD1

command.

•

Entering standby mode when receiving a standby mode

(SPI_CMD2) command.

•

Entering system error mode when an overvoltage or

undervoltage event occurs on Regulator 1, Regulator 2,

Regulator 5, Regulator 10, Regulator 11, or Regulator 12,

and the fault event is not masked in the OV_RST_MASK

when an undervoltage event occurs on the VIO pin, and

the fault event is not masked in the UV_RST_MASK

(WD0, WD1, or QA_WD), and the fault is not masked in

the TRANSITION_MASK register.

•

Entering peripheral error mode when an overvoltage or

undervoltage event occurs on Regulator 3, Regulator 4,

Regulator 6, Regulator 7, Regulator 8, or Regulator 9, and the

fault event is not masked in the OV_FAULT_MASK register

or UV_FAULT_MASK register, or when a fault occurs on

one of the watchdogs (WD0, WD1, or QA_WD), and the

fault is not masked in the TRANSITION_MASK register.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH occurs.

During normal mode, all power rails are turned on, and all

functions are active except for the WAKE function. WD0, WD1,

and the sequenced QA watchdog can be enabled in normal

mode. Different events are mapped to the RESET, FAULT, and

STATUS pins according to the SPI register configurations.

Power-Down Mode

The conditions to enter power-down mode when VAVIN >

VAVIN_UVLO_R, VAVDD > VAVDD_UVLO_R, and VEN > VEN_R include the

following:

•

Entering power-down mode from normal mode when

receiving an SPI_CMD1 command.

•

Entering power-down mode from peripheral error mode

when receiving an SPI_CMD1 command or when

peripheral error counter (PER_EC) ≥ peripheral error

counter threshold (NEC_P).

•

Entering power-down mode from system error mode when

SYS_EC ≥ NEC_S.

The conditions to exit power-down mode include the following:

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH occurs.

During power-down mode, all power rails power down in a

fixed sequence and stay in this mode. SYS_EC and PER_EC

reset. The ADP5140 monitors the input voltage and the die

temperature. The RESET, FAULT, and STATUS pins keep low.

System Error Mode

The conditions to enter system error mode when VAVIN >

VAVIN_UVLO_R, VAVDD > VAVDD_UVLO_R, and VEN > VEN_R include the

following:

•

Entering system error mode from self check mode when

self check mode times out (tEXP1).

•

Entering system error mode from system ramp-up mode

when the system ramp-up times (tEXP2), when an overvoltage

or undervoltage event occurs on Regulator 1, Regulator 2,

Regulator 5, Regulator 10, Regulator 11, or Regulator 12,

or when an overvoltage event occurs on Regulator 1,

Regulator 2, Regulator 5, Regulator 10, Regulator 11, or

Regulator 12, and the fault event is not masked in the

OV_RST_MASK register.

•

Entering system error mode from peripheral ramp-up

mode when an overvoltage or undervoltage event occurs

on Regulator 1, Regulator 2, Regulator 5, Regulator 10,

Regulator 11, or Regulator 12, and the fault event is not

masked in the OV_RST_MASK register or the UV_RST_

MASK register, when SEQ is low, when an undervoltage

event occurs on the VIO pin, and the fault event is not

masked in the UV_RST_MASK register, or when a fault

occurs on one of the watchdogs (WD0, WD1, or QA_WD),

and the fault is not masked in the TRANSITION_MASK

•

Entering system error mode from normal mode when an

overvoltage or undervoltage event occurs on Regulator 1,

Regulator 2, Regulator 5, Regulator 10, Regulator 11, or

Regulator 12, and the fault event is not masked in the

OV_RST_MASK register or the UV_RST_MASK register,

when SEQ is low, or when an undervoltage occurs on the

VIO pin, and the fault event is not masked in the UV_RST_

MASK register, or when a fault occurs on one of the

watchdogs (WD0, WD1, or QA_WD), and the fault is not

masked in the TRANSITION_MASK register.

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ADP5140WACCZ-R7 数据表(PDF) 52 Page - Analog Devices

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