ADP5140WACCZ-R7 datasheet(53/128 Pages) AD

53 / 128 page

Data Sheet

ADP5140

Rev. 0 | Page 53 of 128

•

Entering system error mode from peripheral error mode

when an overvoltage or undervoltage event occurs on

Regulator 1, Regulator 2, Regulator 5, Regulator 10,

Regulator 11, or Regulator 12, and the fault event is not

masked in the OV_RST_MASK register or the UV_RST_

MASK register, when SEQ is low, when an undervoltage

event occurs on the VIO pin, and the fault event is not

masked in the UV_RST_MASK register, or when a fault even

occurs on one of the watchdogs (WD0, WD1, or QA_WD),

and the fault is not masked in the TRANSITION_MASK

•

Entering system error mode from standby mode when an

overvoltage or undervoltage event occurs on any regulator

that is enabled in the standby mode.

The conditions to exit system error mode include the following:

•

Entering power-down mode if SYS_EC ≥ NEC_S.

•

Entering self check mode if SYS_EC < NEC_S and no

overtemperature or overvoltage events occur on any

power rails.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH occurs.

During system error mode, all power rails are turned off. The

ADP5140 monitors the input voltage, the output voltage, and the

die temperature. The system error counter increments. The

RESET, FAULT, and STATUS pins keep low.

System error mode has higher priority than peripheral error

mode. If the exiting condition of any mode meets both the system

error mode and the peripheral mode exiting conditions, the

device enters system error mode instead of peripheral mode.

Peripheral Error Mode

The conditions to enter peripheral error mode when VAVIN >

VAVIN_UVLO_R, VAVDD > VAVDD_UVLO_R, and VEN > VEN_R include the

following:

•

Entering peripheral error mode from peripheral ramp-up

mode when the peripheral ramp-up times out (tEXP3) or

when an overvoltage or undervoltage event occurs on

Regulator 3, Regulator 4, Regulator 6, Regulator 7,

Regulator 8, or Regulator 9.

•

Entering peripheral error mode from normal mode when an

overvoltage or undervoltage event occurs on Regulator 3,

Regulator 4, Regulator 6, Regulator 7, Regulator 8, or

Regulator 9, and the fault event is not masked in the

OV_FAULT_MASK register or the UV_FAULT_MASK

(WD0, WD1, or QA_WD), and the fault is not masked in

the TRANSITION_MASK register.

The conditions to exit peripheral error mode include the

following:

•

Entering power-down mode when receiving an

SPI_CMD1 command or when PER_EC ≥ NEC_P.

•

Entering peripheral ramp-up mode when receiving an

SPI_CMD3 command.

•

Entering system error mode when an overvoltage or

undervoltage event occurs on Regulator 1, Regulator 2,

Regulator 5, Regulator 10, Regulator 11, or Regulator 12,

and the fault event is not masked in the OV_RST_MASK

when an undervoltage event occurs on the VIO pin, and

the fault event is not masked in the UV_RST_MASK register,

or when a fault event occurs on one of the watchdogs

(WD0, WD1, or QA_WD), and the fault is not masked in

the TRANSITION_MASK register.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F,VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH happens.

During peripheral error mode, the peripheral counter increments.

WD0 and the sequenced QA watchdog still work in this mode,

if enabled. The RESET pin is pulled high, and the FAULT and

STATUS pins are pulled low.

Power rail management in the peripheral error mode works

under the following conditions:

•

If a fault on Regulator 3 occurs, Regulator 3, Regulator 4,

Regulator 6, Regulator 7, Regulator 8, and Regulator 9 turn

off, and other regulators still work.

•

If no fault on Regulator 3 occurs, Regulator 4, Regulator 6,

Regulator 7, Regulator 8, and Regulator 9 turn off, and

other regulators still work.

Standby Mode

The ADP5140 enters standby mode from normal mode. The

device receives an SPI_CMD2 command if the WAKE pin is

not pulled low while VAVIN > VAVIN_UVLO_R, VAVDD > VAVDD_UVLO_R,

and VEN > VEN_R.

The conditions to exit standby mode include the following:

•

Entering self check mode when the WAKE pin is driven

low externally during standby mode.

•

Entering system error mode when an overvoltage or

undervoltage event occurs on any regulator that is enabled

in standby mode.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or

VEN < VEN_RGH occurs.

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