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ADP5140WACCZ-R7 数据表(PDF) 9 Page - Analog Devices |
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ADP5140WACCZ-R7 数据表(HTML) 9 Page - Analog Devices |
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9 / 128 page  Data Sheet ADP5140 Rev. 0 | Page 9 of 128 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SEQ SEQ High Voltage Threshold 1.2 1.28 V SEQ Low Voltage Threshold 1.02 1.1 V SEQ Deglitch Time 10 20 µs SEQ Pull-Down Resistance 1 MΩ POWER-UP SEQUENCE Initial Delay tD 3 ms Power-Up Delay 1 tDR1 200 µs Power-Up Delay 2 tDR2 248 µs POWER-DOWN SEQUENCE Power-Down Threshold VMDW On FB11 1.8 V TIMEOUT Self Check Timeout tEXP1 20 ms System Ramp-Up Timeout tEXP2 20 ms Peripheral Ramp-Up Timeout tEXP3 20 ms SPI INTERFACE Input High Threshold CS, SCK, and MOSI 0.7 × VVIO V Input Low Threshold CS, SCK, and MOSI 0.3 × VVIO V MISO High Threshold Source current on the MISO pin (ISOURCE) = 4 mA 0.9 × VVIO V MISO Low Threshold Sink current on the MISO pin (ISINK) = 4 mA 0.1 × VVIO V Maximum SPI Clock Frequency tSCK See Figure 3 and Figure 4 10 MHz SCK Pulse Width High tPWH See Figure 3 45 ns SCK Pulse Width Low tPWL See Figure 3 45 ns CS Falling to SCK Falling Delay Time tDCS See Figure 3 45 ns SCK Rising to CS Rising Delay Time tCSD See Figure 3 45 ns CS High Time tCSH See Figure 3 5 μs Data Setup Time tDS MOSI to SCK, see Figure 3 12.5 ns Data Hold Time tDH MOSI to SCK, see Figure 3 12.5 ns Data Valid Time tDV MISO to SCK, 80 pF load, see Figure 4 27.5 ns |
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