ADP5140WACCZ-R7 datasheet(44/128 Pages) AD

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ADP5140

Data Sheet

Rev. 0 | Page 44 of 128

The watchdog configuration related registers are locked by

default. To unlock these registers, write 1 to the WDTx_LOCK

bit or the QA_WD_LOCK bit in the WDTx_CTRL register or

QA_WD_CTRL register, respectively.

To change the watchdog configuration safely, take the

following steps:

1. Wait until the open window arrives.

2. Feed the watchdog.

3. Unlock the watchdog configuration registers and change

the register values.

4. Wait until the open window arrives.

5. Feed the watchdog so that the new parameters take effect.

PULSE WIDTH MONITOR

The ADP5140 integrates the pulse width monitor circuit to

monitor the pulse width of the signal on the WDIx pins. The

pulse width monitor circuit is disabled by default and can be

enabled through the SPI. The WDIx_PULSE_EN bit in the

WDIx_PULSE_CTRL register controls the pulse width monitor

circuit. Set the WDIx_PULSE_EN bit to enable the pulse width

monitor, and clear the WDIx_PULSE_EN bit to disable the

pulse width monitor.

tWDIx_

PULSE_FAST

tWDIx_PULSE_SLOW

TIME

VWDIx

WINDOW

OPEN

WINDOW

Figure 88. Positive Pulse Width Monitoring

When the pulse width monitor function is enabled, a rising

edge on the WDIx pin resets the pulse width timer and starts

counting until there is a falling edge on the WDIx pin.

The two possible cases for the pulse width monitor fault are as

follows:

•

If the pulse width is smaller than the fast pulse width

(tWDIx_PULSE_FAST) and the WDIx_PULSE_LOWER_MASK bit

in the WDIx_PULSE_CTRL register is 0, a pulse width

fault event occurs.

•

If the pulse width is larger than the slow pulse width

(tWDIx_PULSE_SLOW) and the WDIx_PULSE_UPPER_MASK

bit in the WDIx_PULSE_CTRL register is 0, a pulse width

fault event occurs.

When the pulse width fault event occurs, the relevant bits in the

OTHER_STATUS register and the OTHER_LATCH register

are set.

tWDIx_PULSE_FAST and tWDIx_PULSE_SLOW are programmable through the

SPI, and the equations to calculate the values are as follows:

tWDIx_PULSE_FAST = WDIx_PULSE_LOW × (1 ÷ 2 MHz)

tWDIx_PULSE_SLOW = WDIx_PULSE_HIGH × (1 ÷ 2 MHz)

where:

WDIx_PULSE_LOW is the WDIx_PULSE_LOW register value

in decimal format, and the default value is 850.

WDIx_PULSE_HIGH is the WDIx_PULSE_HIGH register

value in decimal format, and the default value is 1150.

The default values of tWDIx_PULSE_FAST and tWDIx_PULSE_SLOW are

425 µs and 575 µs, respectively.

WDIx PIN AS EXTERNAL EVENTS DETECTION

The WDIx pin can be configured as an external event detection

pin. When configured for the external event detection function,

a low voltage level with a duration time longer than 8 µs on the

WDIx pin sets a latch event in the ADP5140. This latch event is

reflected on the RESET, STATUS, or FAULT pin, depending

on the SPI settings.

An internal 1 MΩ pull-down resistor keeps the voltage on the

WDIx pin below the WDIx low voltage threshold (see Table 1)

when the WDIx pin is left floating.

TSD

Besides the local temperature monitor of each regulator, the

ADP5140 also monitors the central die temperature. If the

central die temperature exceeds the TSD threshold (TSD), the

ADP5140 enters shutdown mode. TSD_HY is included so that the

ADP5140 does not recover from shutdown mode until the

central die temperature drops below TSD – TSD_HY. Upon

recovery, a POR initiates.

RESET, STATUS, AND FAULT FAIL-SAFE PINS

RESET Pin

The RESET pin is an open-drain, bidirectional pin. The RESET pin

is asserted when an event listed in the status registers occurs, and

the corresponding bit in the appropriate mask registers is set to 1.

The status registers include the following:

•

UV_STATUS

•

OV_STATUS

•

WARN_STATUS

•

OT_STATUS

•

OTHER_STATUS

•

OTHER1_STATUS

The mask registers include the following:

•

UV_RST_MASK

•

OV_RST_MASK

•

WARN_RST_MASK

•

OT_RST_MASK

•

OTHER_RST_MASK

•

OTHER1_RST_MASK

ADP5140WACCZ-R7 数据表(PDF) 44 Page - Analog Devices

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