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ADP5140WACCZ-R7 数据表(PDF) 45 Page - Analog Devices |
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ADP5140WACCZ-R7 数据表(HTML) 45 Page - Analog Devices |
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45 / 128 page  Data Sheet ADP5140 Rev. 0 | Page 45 of 128 When the RESET pin is asserted, the pin is pulled low for a reset period time (tRP) and then released. When the RESET pin is asserted, both the FAULT pin and STATUS pin are pulled low. An external low voltage level with a duration time longer than the reset external timeout period (tRESET_EXT) on the RESET pin sets an external pin fail event in the ADP5140. This fail event is reflected on the RESET, STATUS, or FAULT pin, depending on the SPI register settings. If a reset external pin fail event occurs and the RESET_EXT_ FAIL_RST_MASK bit in the OTHER_RST_MASK register is set to 1, the ADP5140 initiates a reset sequence. All power rails restart with the programmed power-up sequence. The reset external timeout period is programmable through the SPI FAIL_SAFE_PIN_TIMEOUT register from 5 µs to 160 µs with a 5 µs step. During power-up, the RESET pin does not pull high until all of the following conditions are met and are followed by a tHOLD delay, as shown in Figure 89: • Regulator 1 (BUCK1) is in regulation. • Regulator 2 (BUCK2) is in regulation. • Regulator 5 (LDO1) is in regulation. • Regulator 10 (LDO6) is in regulation. • Regulator 11 (LDO7) is in regulation. • Regulator 12 (boost) is in regulation. • SEQ is high. • No other system fault event that is mapped on the RESET pin occurs. STATUS Pin The STATUS pin is an open-drain, bidirectional pin. The STATUS pin is asserted (pull low) as long as the latch bit is set to 1 in the appropriate latch registers, and the corresponding bits in the appropriate status pin mask registers are set to 1. The latch registers include the following: • UV_LATCH • OV_LATCH • WARN_LATCH • OT_LATCH • OTHER_LATCH • OTHER1_LATCH Status pin mask registers include the following: • UV_INT_MASK • OV_INT_MASK • WARN_INT_MASK • OT_INT_MASK • OTHER_INT_MASK • OTHER1_INT_MASK An external low voltage level with a duration time longer than the status external time out period (tSTATUS_EXT) on the STATUS pin sets an external pin fail event in the ADP5140. This fail event is reflected on the RESET, STATUS, or FAULT pin, depending on the SPI register settings. The status external timeout period is programmable through the SPI FAIL_SAFE_PIN_TIMEOUT register from 5 µs to 160 µs with a 5 µs step. When the RESET pin is asserted, the STATUS pin is pulled low. The STATUS pin is also controllable through the SPI directly through the SPI_PIN_CTRL register while ignoring the latch and mask register settings. When the STATUS_SPI_CTRL_EN bit is set to 1, the STATUS pin is controlled by the STATUS_ SPI_CTRL_DATA bit value. FAULT Pin The FAULT pin is an open-drain, bidirectional pin. The FAULT pin is asserted (pull low) as long as the latch bit is set to 1 in the latch registers, and the corresponding bits in the appropriate fault pin mask registers are set to 1. See the STATUS Pin section for the list of latch registers used. The fault pin mask registers include: • UV_FAULT_MASK • OV_FAULT_MASK • WARN_FAULT_MASK • OT_FAULT_MASK • OTHER_FAULT_MASK • OTHER1_FAULT_MASK An external low voltage level with a duration time longer than the fault external timeout period (tFAULT_EXT) on the FAULT pin sets an external pin fail event in the ADP5140. This fail event is reflected on the RESET, STATUS, or FAULT pin, depending on the SPI register settings. The fault external time out period is programmable through SPI FAIL_SAFE_PIN_TIMEOUT register from 5 µs to 160 µs with a 5 µs step. When the RESET pin is asserted, the FAULT pin is pulled low. The FAULT pin is also controllable through the SPI directly through the SPI_PIN_CTRL register while ignoring the latch and mask register settings. When the FAULT_SPI_CTRL_EN bit is set to 1, the FAULT pin is controlled by the FAULT_ SPI_CTRL_DATA bit value. |
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