 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADP5140WACCZ-R7 数据表(PDF) 64 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADP5140WACCZ-R7 数据表(HTML) 64 Page - Analog Devices |
|
|
64 / 128 page  ADP5140 Data Sheet Rev. 0 | Page 64 of 128 Table 39. SPI_CNT, Register Address: 0x0014 Bits Bit Name Description Reset Access [31:16] WRITE_CNT SPI Write Counter. 0x0 R [15:0] READ_CNT SPI Read Counter. 0x0 R Table 40. PMIC_PSWD, Register Address: 0x001C Bits Bit Name Description Default Access [31:0] PMIC_PSWD SPI register access is valid only after writing the correct password. However, IF_CFGA, CLR_SPI_CNT, CHIP_INFO1, CHIP_INFO2, SPI_CRC_PARAM, SPI_CNT, PMIC_PSWD, QA_WD_ANSWER, QA_WD_TOKEN, and SCRATCH_PAD are not protected by this password. 0x0 R/W 0x5F6A8C3D: unlock the register access. Other settings: lock the register access. Table 41. QA_WD_ANSWER, Register Address: 0x0020 Bits Bit Name Description Reset Access [31:0] QA_WD_ANSWER Write the correct answer to this register to feed the QA watchdog. 0x0 R/W Table 42. QA_WD_TOKEN, Register Address: 0x0024 Bits Bit Name Description Reset Access [31:4] RESERVED Reserved. 0x0 R [3:0] QA_WD_TOKEN These bits are the token to generate the answer for the QA watchdog. 0x0 R Table 43. SCRATCH_PAD, Register Address: 0x002C Bits Bit Name Description Reset Access [31:0] SCRATCH_PAD Only use this register for read and write register tests. 0x0 R/W Table 44. FAIL_SAFE_PIN_TIMEOUT, Register Address: 0x2000 Bits Bit Name Description Reset Access [31:15] RESERVED Reserved. 0x0 R [14:10] STATUS_TIMEOUT[4:0] Set the Timeout for the STATUS Pin. The range is from 5 µs to 160 µs with 5 µs step. Timeout (µs) = 5 µs + STATUS_TIMEOUT[4:0] × 5 µs. 0x0 R/W [9:5] FAULT_TIMEOUT[4:0] Set the Timeout for the FAULT Pin. The range is from 5 µs to 160 µs with 5 µs step. Timeout (µs) = 5 µs + FAULT_TIMEOUT[4:0] × 5 µs. 0x0 R/W [4:0] RESET_TIMEOUT[4:0] Set the Timeout for the RESET Pin. The range is from 5 µs to 160 µs with 5 µs step. Timeout (µs) = 5 µs + RESET_TIMEOUT[4:0] × 5 µs. 0x0 R/W Table 45. UV_STATUS, Register Address: 0x2004 Bits Bit Name Description Reset Access [31:15] RESERVED Reserved. 0x0 R 14 VIO_UVLO_STATUS Status for the Undervoltage on VIO. 0x0 R 0: no undervoltage fault on VIO. 1: undervoltage fault on VIO. 13 VM1_UV_STATUS Status for the Undervoltage on VM1. 0x0 R 0: no undervoltage on VM1. 1: undervoltage on VM1. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
