ADP5140WACCZ-R7 datasheet(51/128 Pages) AD

51 / 128 page

Data Sheet

ADP5140

Rev. 0 | Page 51 of 128

Initial Mode

The conditions to enter initial mode include the following:

•

Enter initial mode from the POR when VEN is higher than

VEN_RGH (EN_RGH = 1).

•

Enter initial mode from any mode except for shutdown

mode when VAVIN < VAVIN_UVLO_F (AVIN_UVLO = 1), VAVDD

< VAVDD_UVLO_F (AVDD_UVLO = 1), or VEN < VEN_F

(EN_ACC = 0).

The conditions to exit initial mode include the following:

•

Exit initial mode and enter self check mode when initial

mode is completed. Both the VAVIN and VAVDD are higher

than the corresponding UVLO thresholds and VEN > VEN_R.

•

Exit initial mode and enter shutdown mode when the TSD,

the POR, or VEN < VEN_RGH occurs.

In initial mode, the ADP5140 loads the trimmed data and reads

the pin configuration. All power rails turn off and the ADP5140

monitors the input voltage and the die temperature. The

RESET, FAULT, and STATUS pins remain low.

Self Check Mode

The conditions to enter self check mode when VAVIN > VAVIN_UVLO_R

(AVIN_UVLO = 0), VAVDD > VAVDD_UVLO_R(AVDD_UVLO = 0),

and VEN > VEN_R (EN_ACC = 1) include the following:

•

From initial mode when initial mode completes.

•

From standby mode when getting a wake-up signal from

the WAKE pin.

•

From system error mode if the system error counter,

(SYS_EC) < system error counter threshold (NEC_S) and

no overtemperature and overvoltage events happen on any

power rail.

•

From any mode when getting a self check mode from any

mode (SPI_CMD_RST) command.

Conditions of exiting self check mode include the following:

•

Entering system ramp-up mode when self check mode

completes (SELF_CHECK_OK = 1).

•

Entering system error mode when self check mode times

out (tEXP1).

•

Entering initial mode when VAVIN < VAVIN_UVLO_F or VAVDD <

VAVDD_UVLO_F or VEN < VEN_F.

•

Entering shutdown mode when the TSD or the POR or

VEN < VEN_RGH occurs.

During self check mode, the ADP5140 runs the self test and

checks all of the analog and digital circuits for monitoring. All

of the power rails are turned off, and the ADP5140 monitors

the input voltage and the die temperature. SPI registers are

reset in self check mode, except for the SYS_EC. The RESET,

FAULT, and STATUS pins keep low.

System Ramp-Up Mode

The ADP5140 enters system ramp-up mode from self check

mode when the self check completes while VAVIN > VAVIN_UVLO_R,

VAVDD > VAVDD_UVLO_R, and VEN > VEN_R.

The conditions to exit system ramp-up mode include the

following:

•

Entering peripheral ramp-up mode when the system ramp-up

completes (SYS_RAMP_OK = 1) when the SEQ pin is high

and VVIO > VIO_UV (IO_UV = 0).

•

Entering system error mode when the system ramp-up

times out (tEXP2), when an overtemperature event occurs on

Regulator 1, Regulator 2, Regulator 5, Regulator 10,

Regulator 11, or Regulator 12, or an overvoltage event

occurs on Regulator 1, Regulator 2, Regulator 5, Regulator 10,

Regulator 11, or Regulator 12 and the fault event is not

masked in the OV_RST_MASK register.

•

Entering initial mode when VAVIN < VAVIN_UVLO_F, VAVDD <

VAVDD_UVLO_F, or VEN < VEN_F.

•

Entering shutdown mode when the TSD, the POR, or VEN

< VEN_RGH occurs.

During system ramp-up mode, Regulator 1, Regulator 2,

Regulator 5, Regulator 10, Regulator 11, and Regulator 12

power up in a fixed sequence. The RESET, FAULT, and

STATUS pins keep low.

Peripheral Ramp Up Mode

The conditions to enter peripheral ramp-up mode when VAVIN >

VAVIN_UVLO_R, VAVDD > VAVDD_UVLO_R and VEN > VEN_R include the

following:

•

Entering peripheral ramp-up mode from system ramp-up

mode when the system ramp-up completes, the SEQ pin is

high, and VVIO > VIO_UV.

•

Entering peripheral ramp-up mode from peripheral error

mode when receiving a peripheral ramp-up mode

(SPI_CMD3) command.

The conditions to exit peripheral ramp-up mode include the

following:

•

Entering normal mode when peripheral ramp-up mode

completes (PER_RAMP_OK = 1).

•

Entering system error mode when an overvoltage or

undervoltage event occurs on Regulator 1, Regulator 2,

Regulator 5, Regulator 10, Regulator 11, or Regulator 12,

and the fault event is not masked in the OV_RST_MASK

when an undervoltage event occurs on the VIO pin and

the fault event is not masked in the UV_RST_MASK

(WD0, WD1, or QA_WD) and the fault is not masked in

the TRANSITION_MASK register.

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