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ADP5140WACCZ-R7 数据表(PDF) 20 Page - Analog Devices |
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ADP5140WACCZ-R7 数据表(HTML) 20 Page - Analog Devices |
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20 / 128 page  ADP5140 Data Sheet Rev. 0 | Page 20 of 128 Pin No. Mnemonic Description 22 PVIN56 Power Input for LDO1 (Regulator 5) and LDO2 (Regulator 6). 23 OUT6 Output for LDO2 (Regulator 6). 24 FB6 Feedback Voltage Sense Input for LDO2 (Regulator 6). Connect FB6 to OUT6 directly. 25 VREG Regulated Input Supply for IC. Bypass VREG to GND with a ≥1 μF capacitor. Do not connect a load to ground. 26 PVIN9 Power Input for LDO5 (Regulator 9). 27 OUT9 Output for LDO5 (Regulator 9). 28 FB9 Feedback Voltage Sense Input for LDO5 (Regulator 9). Connect FB9 to OUT9 directly. 29 REFCAP Reference Filter for LDO5. Connect a 0.47 μF capacitor between REFCAP and GND. 30 FB8 Feedback Voltage Sense Input for LDO4 (Regulator 8). Connect FB8 to OUT8 directly. 31 OUT8 Output of LDO4 (Regulator 8). 32 PVIN78 Power Input for LDO3 (Regulator 7) and LDO4 (Regulator 8). 33 OUT7 Output of LDO3 (Regulator 7). 34 FB7 Feedback Voltage Sense Input for LDO3 (Regulator 7). Connect FB7 to OUT7 directly. 35 FB4 Feedback Voltage Sense Input for BUCK4. Connect FB4 to OUT4 directly. 36 EN Enable Input. Pull EN high to enable the ADP5140. Connect EN to ground to disable the ADP5140. 37 SEQ Sequence Input Signal. Use SEQ to control the power-up sequence. 38 SW4 Switch Node for BUCK4. 39 PVIN4 Power Input for BUCK4. 40 PVIN3 Power Input for BUCK3. 41 SW3 Switch Node for BUCK3. 42 WAKE Wake-Up Input. 43 FB3 Feedback Voltage Sense Input for BUCK3. Connect FB3 to a resistor divider from the output voltage of BUCK3 (VOUT3). 44 AVIN Analog Voltage Power Supply for Control Circuits. Place a 1 µF ceramic capacitor between AVIN and GND. 45 FB12 Feedback Voltage Sense Input for Boost Regulator. Connect FB12 to OUT12 directly. 46 OUT12 Output of Boost Regulator. 47 SW12 Switch Node for Boost Regulator. 48 CS SPI Chip Select. CS is an active low signal asserted by the SPI master to initiate communication (start of the frame). Deassertion of CS ends the current frame. 49 MISO SPI, Master In, Slave Out. MISO is a push pull output supplied by VVIO. 50 MOSI SPI, Master Out, Slave In. 51 SCK SPI, Clock Driven by the SPI Master. 52 SYNC Synchronization. SYNC can be configured as an input or an output by the SPI, and the default is an input. When configured as an output, SYNC outputs a clock in phase with BUCK1. 53 WDI0 Input for the Watchdog 0 (WD0) Window. 54 WDI1 Input for the Watchdog 1 (WD1) Window. 55 VIO Power Supply for the Digital Interface. 56 FB1 Feedback Voltage Sense Input for BUCK1. Connect FB1 to OUT1 directly. 57 to 62 EP, PGND Exposed PGND Pads. The exposed PGND pads must be soldered to a large, external, copper power ground plane. 63 to 65 EP, GND Exposed GND Pads. The exposed GND pads must be soldered to a large, external, copper power ground plane. |
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