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ADP5140WACCZ-R7 数据表(PDF) 19 Page - Analog Devices |
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ADP5140WACCZ-R7 数据表(HTML) 19 Page - Analog Devices |
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19 / 128 page ![]() Data Sheet ADP5140 Rev. 0 | Page 19 of 128 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 42 VSET1 WAKE GND 65 GND 64 GND 63 PGND 62 PGND 61 PGND 60 PGND 59 PGND 58 PGND 57 SW3 PVIN3 PVIN4 SW4 SEQ EN FB4 FB7 OUT7 PVIN78 OUT8 FB8 REFCAP 41 40 39 38 37 36 35 34 33 32 31 30 29 2 3 4 5 6 7 8 9 10 11 12 13 14 SW1 PVIN1 PVIN2 SW2 PGND MODE FB2 FB10 OUT10 PVIN1011 OUT11 FB11 FAULT ADP5140 TOP VIEW (Not to Scale) NOTES 1. EXPOSED PGND/GND PADS. THE EXPOSED PGND/GND PADS MUST BE SOLDERED TO A LARGE, EXTERNAL, COPPER POWER GROUND PLANE. Figure 5. Pin Configuration (Top View) Table 14. Pin Function Descriptions Pin No. Mnemonic Description 1 VSET1 Output Voltage Setting for BUCK1. Connect a resistor between VSET1 and GND. 2 SW1 Switch Node for BUCK1. 3 PVIN1 Power Input for BUCK1. 4 PVIN2 Power Input for BUCK2. 5 SW2 Switch Node for BUCK2. 6 PGND Power Ground. 7 MODE Connect a resistor between MODE and ground to configure different functions (see the MODE Pin Setting section for more information). The three MODE functions include the following: Enable or disable debug mode. Set the device index of the ADP5140. Selecting of the VIO. 8 FB2 Feedback Voltage Sense Input for BUCK2. Connect FB2 to a resistor divider from the output voltage of BUCK2 (VOUT2). 9 FB10 Feedback Voltage Sense Input for LDO6 (Regulator 10). Connect FB10 to OUT10 directly. 10 OUT10 Output for LDO6 (Regulator 10). 11 PVIN1011 Power Input for LDO6 (Regulator 10) and LDO7 (Regulator 11). 12 OUT11 Output of LDO7 (Regulator 11). 13 FB11 Feedback Voltage Sense Input for LDO7 (Regulator 11). Connect FB11 to OUT11 directly. 14 FAULT Fault Output for the ADP5140. FAULT is bidirectional, open-drain, and active low. 15 RESET Reset Signal for the Processor. RESET is bidirectional, open-drain, and active low. 16 STATUS Status of the ADP5140. STATUS is bidirectional, open-drain, and active low. 17 VM1 Input for Voltage Monitor 1 (VM1). 18 AVDD Supply Voltage for Monitoring Circuits. Place a 1 µF ceramic capacitor between AVDD and GND. 19 VM0 Input for Voltage Monitor 0 (VM0). 20 FB5 Feedback Voltage Sense Input for LDO1 (Regulator 5). Connect FB5 to OUT5 directly. 21 OUT5 Output for LDO1 (Regulator 5). |
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