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ADP5140WACCZ-R7 数据表(PDF) 126 Page - Analog Devices |
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ADP5140WACCZ-R7 数据表(HTML) 126 Page - Analog Devices |
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126 / 128 page  ADP5140 Data Sheet Rev. 0 | Page 126 of 128 Table 126. WAKEPIN_EVT, Register Address: 0x80CC Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. 0x0 R 0 CFG_WAKEPIN_EVT_DET Configure the WAKE Pin Function. 0x0 R/W 0: the WAKE pin is configured as the normal wake function. 1: the WAKE pin is configured as the event detector. Table 127. SYSCRC_EN, Register Address: 0x80D0 Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. 0x0 R 0 SYSCRC_EN System Register CRC Enable Control. 0x0 R/W 0: disable the system register CRC periodic check. 1: enable the system register CRC periodic check. Table 128. VM_TYP_CONFIGURATION, Register Address: 0x80D4 Bits Bit Name Description Reset Access [31:4] RESERVED Reserved. 0x0 R [3:2] VM1_TYP VM1 Typical Configuration. 0x0 R/W 00: neither the undervoltage nor the overvoltage thresholds are effective on VM1. 01: only the undervoltage threshold is effective on VM1. 10: only the overvoltage threshold is effective on VM1. 11: both the undervoltage and the overvoltage thresholds are effective on VM1 and act as window monitors. [1:0] VM0_TYP VM0 Typical Configuration. 0x0 R/W 00: neither the undervoltage nor the overvoltage thresholds are effective on VM0. 01: only the undervoltage threshold is effective on VM0. 10: only the overvoltage threshold is effective on VM0. 11: both the undervoltage and the overvoltage thresholds are effective on VM0 and act as window monitor. Table 129. FUSE_PERIOD_CHK_TIMER, Register Address: 0x80D8 Bits Bit Name Description Reset Access [31:10] RESERVED Reserved. 0x0 R [9:0] FUSE_PERIOD_CHK_TIMER Diagnose Control Block ECC/CRC Periodical Check Timer Counter (ms). 0x96 R/W Table 130. SPI_PIN_CTRL, Register Address: 0x80F0 Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. 0x0 R 3 STATUS_SPI_CTRL_DATA Control STATUS Pin Status. 0x0 R/W 1: high. 0: low. |
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