SPC58EG80C3 datasheet(89/139 Pages) STMICROELECTRONICS

89 / 139 page

DS11758 Rev 6

89/139

SPC584Gx, SPC58EGx, SPC58NGx

Electrical characteristics

106

Figure 27. DSPI PCS strobe (PCSS) timing (master mode)

4.17.2.1.2 DSPI CMOS master mode — modified timing

Note:

In the following table, all output timing is worst case and includes the mismatching of rise

and fall times of the output pads.

PCSx

PCSS

tPCSC

tPASC

Table 48. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1

Symbol

C Characteristic

Condition

Value(1)

Unit

Pad drive(2)

Load (CL)Min

Max

1tSCK CC D SCK cycle time

SCK drive strength

Very strong

25 pF

33.0

—

Strong

50 pF

80.0

—

Medium

50 pF

200.0

—

2tCSC CC D

PCS to SCK

delay

SCK and PCS drive

strength

Very strong

25 pF

(N(3) × tSYS(4))–16

—

Strong

50 pF

(N(3) × tSYS(4))–16

—

Medium

50 pF

(N(3) × tSYS(4))–16

—

PCS

medium and

SCK strong

PCS = 50 pF

SCK = 50 pF

(N(3) × tSYS(4))–29

—

3tASC CC D After SCK delay

SCK and PCS drive

strength

Very strong

PCS = 0 pF

SCK = 50 pF

(M(5) × tSYS(4))– 35

—

Strong

PCS = 0 pF

SCK = 50 pF

(M(5) × tSYS(4))– 35

—

Medium

PCS = 0 pF

SCK = 50 pF

(M(5) × tSYS(4))– 35

—

PCS

medium and

SCK strong

PCS = 0 pF

SCK = 50 pF

(M(5) × tSYS(4))– 35

—

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