SPC58EG80C3 datasheet(12/139 Pages) STMICROELECTRONICS

12 / 139 page

Description

SPC584Gx, SPC58EGx, SPC58NGx

12/139

DS11758 Rev 6

2.3

Features

On-chip modules within SPC584Gx, SPC58EGx, SPC58NGx include the following features:

•

Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), one paired in

lock-step

–

Power architecture embedded specification compliance

–

Instruction set enhancement allowing variable length encoding (VLE), encoding a

mix of 16-bit and 32-bit instructions, for code size footprint reduction

–

Single-precision floating point operations

–

Lightweight signal processing auxiliary processing unit (LSP APU) instruction

support for digital signal processing (DSP) on Core_2

–

16 KB local instruction RAM and 64 KB local data RAM for Core_0 and Core_1,

16 KB local instruction RAM and 32 KB local data RAM for Core_2

–

8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_1, 8kB I-Cache for Core_2

•

6400 KB (6144 KB code flash + 256 KB data flash) on-chip Flash memory

–

Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

–

Supports read while read between the two code Flash partitions

•

608 KB on-chip general-purpose SRAM (+ 160 KB data RAM included in the CPUs)

•

182 KB HSM dedicated flash memory (144 KB code + 32 KB data)

•

Multi channel direct memory access controllers (eDMA paired in lock-step)

–

One eDMA with 64 channels

–

One eDMA with 32 channels

•

One interrupt controller (INTC) in lock-step

•

Dual phase-locked loops with stable clock domain for peripherals and FM modulation

domain for computational shell

•

Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM

from multiple bus masters with end-to-end ECC

•

Hardware security module (HSM) to provide robust integrity checking of Flash memory

•

System integration unit lite (SIUL)

•

Boot assist Flash (BAF) supports factory programming using a serial bootload through

the asynchronous CAN or LIN/UART

•

Hardware support for motor control and safety related applications

•

Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with

16-bit counter resolution

–

Buffered updates

–

Support for shifted PWM outputs to minimize occurrence of concurrent edges

–

Supports configurable trigger outputs for ADC conversion for synchronization to

channel output waveforms

–

Shared or independent time bases

–

DMA transfer support available

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