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SPC58EG80C3 数据表(PDF) 93 Page - STMicroelectronics |
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SPC58EG80C3 数据表(HTML) 93 Page - STMicroelectronics |
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93 / 139 page  DS11758 Rev 6 93/139 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 106 Figure 30. DSPI PCS strobe (PCSS) timing (master mode) 4.17.2.2 Slave mode timing PCSx PCSS tPCSC tPASC Table 49. DSPI CMOS slave timing — full duplex — normal and modified transfer formats (MTFE = 0/1) # Symbol C Characteristic Condition Min Max Unit Pad Drive Load 1tSCK CC D SCK Cycle Time(1) —— 62 — ns 2tCSC SR D SS to SCK Delay(1) —— 16 — ns 3tASC SR D SCK to SS Delay(1) —— 16 — ns 4tSDC CC D SCK Duty Cycle(1) —— 30 — ns 5tA CC D Slave Access Time(1) (2) (3) (SS active to SOUT driven) Very strong 25 pF — 50 ns Strong 50 pF — 50 ns Medium 50 pF — 60 ns 6tDIS CC D Slave SOUT Disable Time(1) (2) (3) (SS inactive to SOUT High- Z or invalid) Very strong 25 pF — 5 ns Strong 50 pF — 5 ns Medium 50 pF — 10 ns 9tSUI CC D Data Setup Time for Inputs(1) —— 10 — ns 10 tHI CC D Data Hold Time for Inputs(1) —— 10 — ns 11 tSUO CC D SOUT Valid Time(1) (2) (3) (after SCK edge) Very strong 25 pF — 30 ns Strong 50 pF — 30 ns Medium 50 pF — 50 ns 12 tHO CC D SOUT Hold Time(1) (2) (3) (after SCK edge) Very strong 25 pF 2.5 — ns Strong 50 pF 2.5 — ns Medium 50 pF 2.5 — ns 1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 2. All timing values for output signals in this table, are measured to 50% of the output voltage. 3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. |
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