SPC58EG80C3 datasheet(99/139 Pages) STMICROELECTRONICS

99 / 139 page

DS11758 Rev 6

99/139

SPC584Gx, SPC58EGx, SPC58NGx

Electrical characteristics

106

Note:

In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the

valid input levels, 0.8 V and 2.0 V.

Figure 38. RMII receive signal timing diagram

4.17.3.7

RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK

frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the

rising or falling edge of REF_CLK, and the timing is the same in either case. This option

allows the use of non-compliant RMII PHYs.

Note:

In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the

valid output levels, 0.8 V and 2.0 V.

RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on

the pad as 1ns.

Table 55. RMII receive signal timing

Symbol

Characteristic

Value

Unit

Min

Max

CC D RXD[1:0], CRS_DV to REF_CLK setup

—

CC D REF_CLK to RXD[1:0], CRS_DV hold

—

CC D REF_CLK pulse width high

35%

65%

REF_CLK period

CC D REF_CLK pulse width low

35%

65%

REF_CLK period

REF_CLK (input)

RXD[1:0] (inputs)

CRS_DV

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