 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
SPC58EG80C3 数据表(PDF) 91 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC58EG80C3 数据表(HTML) 91 Page - STMicroelectronics |
|
|
91 / 139 page  DS11758 Rev 6 91/139 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 106 SOUT data valid time (after SCK edge) 9tSUO CC D SOUT data valid time from SCK CPHA = 0, (10) SOUT and SCK drive strength Very strong 25pF — 7.0+tSYS(4) ns Strong 50 pF — 8.0 + tSYS(4) Medium 50 pF — 16.0 + tSYS(4) SOUT data valid time from SCK CPHA = 1(10) SOUT and SCK drive strength Very strong 25 pF — 7.0 ns Strong 50 pF — 8.0 Medium 50 pF — 16.0 SOUT data hold time (after SCK edge) 10 tHO CC D SOUT data hold time after SCK CPHA = 0(10) SOUT and SCK drive strength Very strong 25pF –7.7+tSYS(4) — ns Strong 50 pF –11.0 + tSYS(4) — Medium 50 pF –15.0 + tSYS(4) — SOUT data hold time after SCK CPHA = 1(10) SOUT and SCK drive strength Very strong 25 pF –7.7 — ns Strong 50 pF –11.0 — Medium 50 pF –15.0 — 1. All timing values for output signals in this table are measured to 50% of the output voltage. 2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS =10 ns). 5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 7. PCSx and PCSS using same pad configuration. 8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds. 9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_ MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. Table 48. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1 (continued) # Symbol C Characteristic Condition Value(1) Unit Pad drive(2) Load (CL)Min Max |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
