SPC58EG80C3 datasheet(98/139 Pages) STMICROELECTRONICS

98 / 139 page

Electrical characteristics

SPC584Gx, SPC58EGx, SPC58NGx

98/139

DS11758 Rev 6

Note:

In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)

to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is

referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.

Figure 37. MII serial management channel timing diagram

4.17.3.6

RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK

frequency.

Table 54. RMII serial management channel timing

Symbol

Characteristic

Value

Unit

Min

Max

M10

CC D

MDC falling edge to MDIO output invalid

(minimum propagation delay)

0—

M11

CC D

MDC falling edge to MDIO output valid (max

prop delay)

—25

M12

CC D MDIO (input) to MDC rising edge setup

—

M13

CC D MDIO (input) to MDC rising edge hold

—

M14

CC D MDC pulse width high

40%

60%

MDC period

M15

CC D MDC pulse width low

40%

60%

MDC period

M11

MDC (output)

MDIO (output)

M12

M13

MDIO (input)

M10

M14

M15

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