C5C5EDELTA-RMSLASHD datasheet(109/114 Pages) NXP

109 / 114 page

C3ENPA1-DS/D

Rev 03

INDEX

Symbols

10/100 Ethernet (RMII) Configuration 35

10/100 Ethernet Signals 35

10/100 Ethernet Timing Description 82

10/100 Ethernet Timing Diagram 82

10/100 Ethernet Timing Specifications 82

Absolute Maximum Ratings 71

AC Timing Specifications 79

Block Diagram, C-3e Network Processor 20

BMU SDRAM Interface Signals 51

BMU Signal Groups 95

BMU Timing Description 94

BMU Timing Diagram 94

BMU Timing Specifications 94

Boundary Scan Cell Types 67

Boundary Scan Description Language 70

Bringup Clock Timing Diagram 74

Buffer Management Unit 24

C-3e Network Processor Absolute Maximum Ratings 71

C-3e Network Processor BGA Package, Bottom View 104

C-3e Network Processor BGA Package, Side View 103

C-3e Network Processor Capacitance Data 73

C-3e Network Processor DC Characteristics 73

C3e Network Processor Power and Thermal Characteristics 75

C-3e NP Channel Processors 22

Channel Processor Interface Signals 31

Channel Processors 22

Channel Processors Physical Interface Signals and Pins

Grouped by Clusters 33

Clock and Reference Signals 31

Clock Signals 31

Clock Timing Specifications 80

Configuration

10/100 Ethernet (RMII) 35

DS1/T1 Framer Interface 34

FibreChannel TBI 38

Gigabit Ethernet 38

Gigabit Ethernet (GMII) 36

SONET OC-12 Transceiver Interface 41

SONET OC-3 Transceiver Interface 40

Configurations

GMII/TBI Transmit and Receive Pin 36

CP Timing Specifications 81

Data Registers

JTAG 67

DC Characteristics 73

Description

Functional 19

Description Language

Boundary Scan 70

Descriptions

Signal 27

Diagram

10/100 Ethernet Timing 82

BMU Timing 94

Bringup Clock Timing 74

DS1/DS3 Ethernet Timing 81

Fabric Processor Timing 92

Gigabit Ethernet (TBI) Timing 83

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

C5C5EDELTA-RM/D 数据表(PDF) 109 Page - NXP Semiconductors

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