C5C5EDELTA-RMSLASHD datasheet(111/114 Pages) NXP

111 / 114 page

INDEX

111

Miscellaneous Test Signals for JTAG, Scan, and Internal Test

Routines 57

OC-12 Signals 41

OC-12 Timing Description 86

OC-12 Timing Specifications 86

OC-3 Signals 40

OC-3 Timing Description 85

OC-3 Timing Diagram 85

OC-3 Timing Specifications 85

Operating Conditions, Recommended 72

Package Measurements 106

PCI Signals 43

PCI Timing Description 88

PCI Timing Diagram 87

PCI Timing Specifications 87

Pin Descriptions

Grouped by Function 30

Pin Locations 28

Pin Number Signals Groups 58

Pinout Diagram 28

Power Sequencing 74, 75

Power Supply Signals 56

Processor, Executive 23

Processor, Fabric 24

PROM Interface Diagram 46

PROM Interface Signals 45

PROM Interface Timing Description 91

PROM Interface Timing Diagram 91

PROM Interface Timing Outline 47

PROM Interface Timing Specifications 91

QMU Signal Groups 99

QMU SRAM (Internal Mode) Timing Diagram 98

QMU SRAM Interface Signals 54, 55

QMU Timing Description 98

QMU Timing Specifications 98

QMU to Q-5/Q-3 (External Mode) Timing Diagram 100

Queue Management Unit 26

Recommended Operating Conditions 72

IDcode 69

JTAG Instruction 69

Serial Interface Signals 44

Serial Port Signals 44

Signal

General System Interface 48

Signal Descriptions 27

Signal Summary 27

Signals

10/100 Ethernet 35

BMU SDRAM Interface 51

Channel Processor Interface 31

Clock 31

Clock and Reference 31

DS1/T1 Framer Interface 34

Fabric Processor Interface 49

Grouped by Pin Number 58

OC-12 41

OC-3 40

PCI 43

Power Supply 56

PROM Interface 45

QMU SRAM Interface 54, 55

Serial Interface 44

Serial Port 44

Test 57

TLU SRAM Interface 53

SONET OC-12 Transceiver Interface Configuration 41

SONET OC-3 Transceiver Interface Configuration 40

Specifications

10/100 Ethernet Timing 82

AC Timing 79

BMU Timing 94

Clock Timing 80

CP Timing 81

DS1/DS3 Timing 81

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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