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STM32H7B3AI 数据表(PDF) 113 Page - STMicroelectronics |
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STM32H7B3AI 数据表(HTML) 113 Page - STMicroelectronics |
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113 / 238 page  Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit Jitter Cycle-to-cycle jitter fVCO_OUT = 560 MHz ±ps - 15 - Long term jitter Normal mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz - ±0.2 - % Normal mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz - ±0.8 - Sigma-delta mode (f PLL_IN = 2 MHz), fVCO_OUT = 560 MHz - ±0.2 - Sigma-delta mode (f PLL_IN = 16 MHz), fVCO_OUT = 560 MHz - ±0.8 - IDD(PLL) PLL power consumption fVCO_OUT = 560 MHz VDD - 330 420 µA VCORE - 630 - fVCO_OUT = 128 MHz VDD - 155 230 VCORE - 170 - 1. Guaranteed by design, unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Guaranteed by characterization results. Table 56. PLL characteristics (medium VCO frequency range) Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit fPLL_IN PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % fPLL_OUT PLL multiplier output clock P, Q, R VOS0 1.17 - 210 MHz VOS1 1.17 - 210 VOS2 1.17 - 160(2) VOS3 1.17 - 88(2) fVCO_OUT PLL VCO output - 150 - 420 tLOCK PLL lock time Normal mode - 45 80(3) µs Sigma-delta mode forbidden Jitter Cycle-to-cycle jitter fVCO_OUT = 150 MHz - - 60 - ±ps fVCO_OUT = 200 MHz - - 40 - fVCO_OUT = 400 MHz - - 18 - fVCO_OUT = 420 MHz - - 15 - Period jitter fVCO_OUT = 150 MHz fPLL_OUT = 50 MHz - 75 - ±-ps fVCO_OUT = 400 MHz - 25 - Long term jitter Normal mode, fVCO_OUT = 400 MHz - ±0.2 - % IDD(PLL) PLL power consumption on VDD fVCO_OUT = 420 MHz VDD - 275 360 µA VCORE - 450 - fVCO_OUT = 150 MHz VDD - 160 240 VCORE - 165 - 1. Guaranteed by design, unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Guaranteed by characterization results. STM32H7B3xI Operating conditions DS13139 - Rev 8 page 113/238 |
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