CS5535 datasheet(210/555 Pages) NSC

210 / 555 page

www.national.com

210

Revision 0.8

GLIU Register Descriptions (Continued)

5.1.4

IOD Descriptor MSRs

5.1.4.1

IOD Base Mask Descriptors (GLIU_IOD_BM[x])

IOD Base Mask 0 (GLIU_IOD_BM0)

IOD Base Mask 1 (GLIU_IOD_BM1)

IOD Base Mask 2 (GLIU_IOD_BM2)

IOD Base Mask 3 (GLIU_IOD_BM3)

IOD Base Mask 4 (GLIU_IOD_BM4)

IOD Base Mask 5 (GLIU_IOD_BM5)

IOD Base Mask 6 (GLIU_IOD_BM6)

IOD Base Mask 7 (GLIU_IOD_BM7)

IOD Base Mask 8 (GLIU_IOD_BM8)

IOD Base Mask 9 (GLIU_IOD_BM9)

MSR Address

510100E0h

Type

R/W

Reset Value

60000000_1F0FFFF0h

MSR Address

510100E1h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E2h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E3h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E4h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E5h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E6h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E7h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E8h

Type

R/W

Reset Value

000000FF_FFF00000h

MSR Address

510100E9h

Type

R/W

Reset Value

000000FF_FFF00000h

GLIU_IOD_BM[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

IDID_BM

RSVD

IBASE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

IBASE_BM

IMASK_BM

GLIU_IOD_BM[x] Bit Descriptions

Bit

Name

Description

63:61

IDID_BM

I/O Descriptor Destination ID. These bits define which port to route the request to if it is

a hit based on the other settings in this register.

000: Port 0 (GLIU)

100: Port 4 (DD)

001: Port 1 (GLPCI_SB)

101: Port 5 (ACC)

010: Port 2 (USBC2)

110: Port 6 (USBC1)

011: Port 3 (ATAC)

111: Port 7 (GLCP)

ICMP_BIZ_BM

Compare BIZZARO Flag.

0: Consider only transactions whose BIZZARO flag is low as a potentially valid address

hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or

I/O.

1: Consider only transactions whose BIZZARO flag is high as a potentially valid address

hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or

Halt cycle.

CS5535 数据表(PDF) 210 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 210 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5535 数据表(PDF) 210 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 210 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载