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CS5535 数据表(PDF) 213 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 213 Page - National Semiconductor (TI) |
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213 / 555 page  Revision 0.8 213 www.national.com 5.2 GEODELINK PCI SOUTH BRIDGE REGISTER DESCRIPTIONS The GeodeLink PCI South Bridge (GLPCI_SB) register set consists of: • Standard GeodeLink Device MSRs • GLPCI_SB Specific MSRs • PCI Configuration Registers The MSRs (both Standard and GLPCI_SB Specific) are accessed via the RDMSR and WRMSR processor instruc- tions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. Additionally, all GLPCI_SB Specific MSRs can be accessed through both the PCI and GLIU interfaces. See Section 5.2.3 "PCI Configuration Registers" on page 225 for details. The PCI configuration registers can only be accessed through the PCI interface and include: • The first 16 bytes of standard PCI configuration regis- ters. • MSR access registers: —PMCTRL — PMADDR —PMDATA0 —PMDATA1 Tables 5-5 through 5-7 are register summary tables that include reset values and page references where the bit descriptions are provided. Table 5-5. Standard GeodeLink Device MSRs Summary MSR Address Type Register Reset Value Reference 51000000h RO GeodeLink Device Capabilities MSR (GLPCI_GLD_MSR_CAP) 00000000_002051xxh Page 214 51000001h R/W GeodeLink Device Master Configuration MSR (GLPCI_GLD_MSR_CONFIG) 00000000_00000000h Page 215 51000002h R/W GeodeLink Device SMI MSR (GLPCI_GLD_MSR_SMI) 00000000_00000000h Page 215 51000003h R/W GeodeLink Device Error MSR (GLPCI_GLD_MSR_ERROR) 00000000_00000000h Page 216 51000004h R/W GeodeLink Device Power Management MSR (GLPCI_GLD_MSR_PM) 00000000_00000000h Page 218 51000005h R/W GeodeLink Device Diagnostic MSR (GLPCI_GLD_MSR_DIAG) 00000000_00000000h Page 219 Table 5-6. GLPCI_SB Specific MSRs Summary MSR Address Type Register Reset Value Reference 51000010h R/W Global Control (GLPCI_CTRL) 44000030_00000003h Page 219 51000020h R/W Region 0 Configuration (GLPCI_R0) 00000000_00000000h Page 223 51000021h R/W Region 1 Configuration (GLPCI_R1) 00000000_00000000h Page 223 51000022h R/W Region 2 Configuration (GLPCI_R2) 00000000_00000000h Page 223 51000023h R/W Region 3 Configuration (GLPCI_R3) 00000000_00000000h Page 223 51000024h R/W Region 4 Configuration (GLPCI_R4) 00000000_00000000h Page 223 51000025h R/W Region 5 Configuration (GLPCI_R5) 00000000_00000000h Page 223 51000026h R/W Region 6 Configuration (GLPCI_R6) 00000000_00000000h Page 223 51000027h R/W Region 7 Configuration (GLPCI_R7) 00000000_00000000h Page 223 51000028h R/W Region 8 Configuration (GLPCI_R8) 00000000_00000000h Page 223 51000029h R/W Region 9 Configuration (GLPCI_R9) 00000000_00000000h Page 223 5100002Ah R/W Region 10 Configuration (GLPCI_R10) 00000000_00000000h Page 223 5100002Bh R/W Region 11 Configuration (GLPCI_R11) 00000000_00000000h Page 223 5100002Ch R/W Region 12 Configuration (GLPCI_R12) 00000000_00000000h Page 223 |
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