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CS5535 数据表(PDF) 270 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 270 Page - National Semiconductor (TI) |
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270 / 555 page  www.national.com 270 Revision 0.8 USB Register Descriptions (Continued) 5.5.3 USB Embedded PCI Configuration Registers 5.5.3.1 Vendor Identification (USBC_PCI_ VENID) 5.5.3.2 Device Identification (USBC_PCI_DEVID) 16:14 RCVR2_VADJ Single Ended Receiver #2 Threshold Voltage Adjustment. For proper operation this must be set to 100 (4h). See electrical specifications Section 6.3.6 "USB Signals" on page 540. 13:9 XMIT2_CADJ Differential Transmitter #2 Slew Rate Current Adjustment. For proper operation this must be set to 010 (2h). See electrical specifications Section 6.3.6 "USB Signals" on page 540. 8XCEIV1_PM Transceiver 1 Power Management Bit. Disables transceiver #1 and puts the trans- ceiver in a low power state. 0: Enable transceiver. 1: Disable transceiver. 7:5 RCVR1_VADJ Single Ended Receiver #1 Threshold Voltage Adjustment. For proper operation this must be set to 100 (4h). See electrical specifications Section 6.3.6 "USB Signals" on page 540. 4:0 XMIT1_CADJ Differential Transmitter #1 Slew Rate Current Adjustment. For proper operation this must be set to 010 (2h). See electrical specifications Section 6.3.6 "USB Signals" on page 540. Index 00h Type RO Reset Value 0E11h USBC_XCVR Bit Description Bit Name Description USBC_PCI_VENID Register Map 15 14 13 12 11 10 9876 5432 10 VENDOR_ID USBC_PCI_VENID Bit Descriptions Bit Name Description 15:0 VENDOR_ID Vendor ID. Index 02h Type RO Reset Value A0F8h USBC_DEVID Register Map 15 14 13 12 11 10 9876 5432 10 DEVICE_ID USBC_DEVID Bit Descriptions Bit Name Description 15:0 DEVICE_ID Device ID. |
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