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CS5535 数据表(PDF) 273 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 273 Page - National Semiconductor (TI) |
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273 / 555 page  Revision 0.8 273 www.national.com USB Register Descriptions (Continued) 5.5.3.7 Cache Line Size (USBC_PCI_CACHE) 5.5.3.8 Latency Timer (USBC_PCI_LTNCY_TMR) 5.5.3.9 Header Type (USBC_PCI_HEADER) USBC_PCI_CLASS Bit Descriptions Bit Name Description 23:0 PCI_CLASS PCI Class. This register identifies this function as an OpenHCI device. The base class is 0Ch (serial bus controller). The sub class is 03h (universal serial bus). The program- ming interface is 10h (OpenHCI). Index 0Ch Type R/W Reset Value 00h USBC_PCI_CACHE Register Map 76 54 32 10 PCI_CACHE USBC_PCI_CACHE Bit Descriptions Bit Name Description 7:0 PCI_CACHE PCI Cache. The USB controller stores the system cache line size, in units of 32-bit WORDs in bit 3 of this register. A cache line size of 32 bytes is the only one applicable to this design. Users must set this register to 08h for proper operation. Any value other than 08h written to this register is read back as 00h. Index 0Dh Type R/W Reset Value 00h USBC_PCI_LTNCY_TMR Register Map 76 54 32 10 LTNCY_TMR USBC_PCI_LTNCY_TMR Bit Descriptions Bit Name Description 7:0 LTNCY_TMR Latency Timer. This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Index 0Eh Type RO Reset Value 00h USBC_PCI_HEADER Register Map 76 54 32 10 PCI_HEADER |
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