CS5535 datasheet(303/555 Pages) NSC

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DIVIL Register Descriptions (Continued)

5.6.1.4

GeodeLink Device Error MSR (DIVIL_GLD_MSR_ERROR)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.4 "MSR Address 3: Error Control" on page 71

for further on ERR generation details.)

PIC_ASMI_EN

PIC ASMI Enable. Write 1 to enable PIC_ASMI_FLAG (bit 35) and to allow the

Extended PIC Mapper to generate an ASMI.

KEL_EE_ASMI_

KEL Emulation Event ASMI Enable. Write 1 to enable KEL_EE_ASMI_FLAG (bit 34)

and to allow the KEL to generate an ASMI.

SHTDWN_ASMI_

Shutdown ASMI Enable. Write 1 to enable SHTDWN_ASMI_FLAG (bit 33) and to

allow a Shutdown special cycle to generate an ASMI.

0HLT_ASMI_EN

Halt ASMI Enable. Write 1 to enable HLT_ASMI_FLAG (bit 32) and to allow a Halt spe-

cial cycle to generate an ASMI.

MSR Address

51400003h

Type

R/W

Reset Value

00000000_00000000h

DIVIL_GLD_MSR_ERROR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

DIVIL_GLD_MSR_ERROR Bit Descriptions

Bit

Name

Description

63:55

RSVD

Reserved. Reads return 0. Writes have no effect.

UART1XUART2_

ERR_FLAG

UART1 and UART2 Error Flag. If high, records that an ERR was generated due to a

collision between the two UARTs. UART1 and UART2 are set to the same I/O address

base. No chip selects are asserted and DECODE_ERR_FLAG (bit 33) is asserted.

DECODE_ERR_EN (bit 1) must be high to generate ERR and set flag. Write 1 to clear;

writing 0 has no effect.

DIVIL_GLD_MSR_SMI Bit Descriptions (Continued)

Bit

Name

Description

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