GD32F310 datasheet(17/81 Pages) GIGADEVICE

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GD32F310xx Datasheet

2.5

Clock tree

Figure 2-7. GD32F310xx clock tree

4- 32 MHz

HXTAL

8 MHz

IRC8M

×2,3,4

,64

PLL

Clock

Monit or

PLLSEL

PREDV

CK_IRC8M

CK_HXTAL

CK_PLL

CK_ SYS

72 MHz max

AHB

Prescaler

÷1,2... 512

CK_ AHB

72 MHz max

APB1

Prescaler

÷1,2,4,8,16

TIMER1,2,5,13

if(APB1 prescaler

=1) = AHB

else

= AHB / (APB1

prescaler /2)

APB2

Prescaler

÷1,2,4,8,16

CK_ APB2

36 MHz max

Peripheral enable

PCLK2

to APB2 peripherals

CK_ APB1

36 MHz max

Peripheral enable

PCLK1

to APB1 peripherals

TIMERx

enable

CK_TIMERx

to TIMER0,14,15,16

TIMERx

enable

CK_TIMERx

to TIMER 2,13

AHB enable

HCLK

( to AHB bus, Cortex-M4, SRAM, DMA)

FMC enable

( by hardware)

CK_FMC

( to FMC)

÷8

CK_ CST

( to Cortex-M 4 SysTick)

FCLK

( free running clock

)

32. 768 KHz

LXTAL

40 KHz

IRC40K

CK_ RTC

CK_F WDGT

( to RTC)

( to F WDGT)

/32

CK_ LXTAL

CK_PLL

CK_ HXTAL

CK_ IRC8M

CK_ OUT

SCS[1:0]

RTCSRC[1:0]

÷1,2.

..16

CK_I2S

(to I2S)

CK_SYS

CK_ IRC40K

CK_IRC28M

/1,2

÷1,2,4... 128

CKOUTDIV

48 MHz

IRC48M

CTC

CK_ CTC

CK_ IRC48M

CK_IRC48M

PLLPRESEL

PLLMF

IRC

XTAL

CK_

CK SYS

CK USART

to USART

28 MHz

28M

IRC

CK_ ADC to ADC

40 MHz max

ADCSEL

ADC

Prescaler

÷ ,

3 5,

ADC

Prescaler

÷ ,

2 4, ,

6 8

7,9

÷ 2

TIMER0,14,15,16

if(APB2 prescaler

=1) = AHB

else

= AHB / (APB2

prescaler /2)

Note:

If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1.

Otherwise, they are set to the AHB frequency divide by half of APB prescaler.

Legend:

HXTAL: High speed crystal oscillator

LXTAL: Low speed crystal oscillator

IRC8M: Internal 8M RC oscillators

IRC40K: Internal 40K RC oscillator

IRC48M: Internal 48M RC oscillator

IRC28M: Internal 28M RC oscillators

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