GD32F310 datasheet(34/81 Pages) GIGADEVICE

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GD32F310xx Datasheet

no waiting time within code Flash area when CPU executes instructions. Table 2-3.

GD32F310xx memory map shows the memory map of the GD32F310xx series of devices,

including code, SRAM, peripheral, and other pre-defined regions.

3.3

Clock, reset and supply management



Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator

 Internal 48 MHz RC oscillator



Internal 28 MHz RC oscillator



Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator



Integrated system clock PLL



2.6 to 3.6 V application supply and I/Os



Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage

detector (LVD)

The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These

include speed internal RC oscillator and external crystal oscillator, high speed and low speed

two types. Several prescalers allow the frequency configuration of the AHB and two APB

domains. The maximum frequency of the AHB, APB2 and APB1 domains is 72 MHz/36

MHz/36 MHz

. See Figure 2-7. GD32F310xx clock tree for details on the clock tree.

The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor

core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are

always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device

remains in reset mode when VDD is below a specified threshold

. The embedded low voltage

detector (LVD) monitors the power supply, compares it to the voltage threshold and generates

an interrupt as a warning message for leading the MCU into security.

Power supply schemes:



VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.



VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,

RCs and PLL.



VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and

backup registers (through power switch) when VDD is not present.

3.4

Boot modes

At startup, boot pins are used to select one of three boot options:



Boot from main Flash memory (default)



Boot from system memory



Boot from on-chip SRAM

In default condition, boot from main Flash memory is selected. The boot loader is located in

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