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GD32F310 数据表(PDF) 63 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32F310 数据表(HTML) 63 Page - GigaDevice Semiconductor (Beijing) Inc. |
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63 / 81 page ![]() GD32F310xx Datasheet 62 Figure 4-9. I2S timing diagram - master mode tCK D[0] D[0] tH tL tSU(SD_MR) tH(SD_MR) tV(SD_MT) tH(SD_MT) CPOL=0 CPOL=1 WS output SD transmit SD receive tV(WS) tH(WS) Figure 4-10. I2S timing diagram - slave mode tCK D[0] D[0] tH tL tSU(SD_SR) tH(SD_SR) tV(SD_ST) tH(SD_ST) CPOL=0 CPOL=1 WS input SD transmit SD receive tH(WS) tSU(WS) |
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