GD32F310 datasheet(60/81 Pages) GIGADEVICE

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GD32F310xx Datasheet

(3)

The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the

falling edge of SCL

Figure 4-6. I2C bus timing diagram

4.16

SPI characteristics

Table 4-35

. Standard SPI characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK(1)

SCK clock frequency

—

MHz

tSCK(H) (1)

SCK clock high time

Master mode, fPCLKx = 72 MHz

25.78 27.78 29.78

tSCK(L) (1)

SCK clock low time

Master mode, fPCLKx = 72 MHz

25.78 27.78 29.78

SPI master mode

tV(MO)(2)

Data output valid time

—

6.67

—

tH(MO)(2)

Data output hold time

—

5.67

—

tSU(MI)(1)

Data input setup time

—

tH(MI) (1)

Data input hold time

—

SPI slave mode

tSU(NSS)(1)

NSS enable setup time

—

tH(NSS)(1)

NSS enable hold time

—

tA(SO)(2)

Data output access time

—

10.8

—

tDIS(SO)(2)

Data output disable time

—

15.5

—

tV(SO)(2)

Data output valid time

—

13.5

—

tH(SO)(2)

Data output hold time

—

11.1

—

tSU(SI) (1)

Data input setup time

—

tH(SI) (1)

Data input hold time

—

(1)

Guaranteed by design, not tested in production.

(2)

Based on characterization, not tested in production.

70%

30%

tF(SDA)

30%

70%

tR(SDA)

tH(STA)

tSCL(L)

tSCL(H)

tR(SCL)

tF(SCL)

tH(SDA)

tSU(SDA)

SDA

SCL

tBUFF

tSU(STA)

tSU(STO)

70%

30%

70%

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