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GD32F310xx Datasheet

VDD

Supply voltage

—

2.6

3.3

3.6

VDDA

Analog supply voltage

Same as VDD

2.6

3.3

3.6

VBAT

Battery supply voltage

—

1.8(2)

—

3.6

(1)

Based on characterization, not tested in production.

(2)

In the application which VBAT supply the backup domains, if the VBAT voltage drops below the minimum value,

when VDD is powered on again, it is necessary to refresh the registers of backup domains and enable LXTAL

again.

Figure 4-1. Recommended power supply decoupling capacitors(1)

100 nF

VBAT

VSS

N * VDD

VSS

4.7

μF + N * 100 nF

10 nF

VDDA

VSSA

μF

(1)

All decoupling capacitors need to be as close as possible to the pins on the PCB board. More details refer to

AN057 GD32F3x0 Hardware Development Guide.

Table 4-3. Clock frequency(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fHCLK1

AHB1 clock frequency

—

MHz

fHCLK2

AHB2 clock frequency

—

MHz

fAPB1

APB1 clock frequency

—

MHz

fAPB2

APB2 clock frequency

—

MHz

(1)

Guaranteed by design, not tested in production.

Table 4-4. Operating conditions at Power up/ Power down(1)

Symbol

Parameter

Conditions

Min

Max

Unit

tVDD

VDD rise time rate

—

∞

μs /V

VDD fall time rate

∞

(1)

Guaranteed by design, not tested in production.

Table 4-5. Start-up timings of Operating conditions(1)(2)(3)

Symbol

Parameter

Conditions

Typ

Unit

tstart-up

Start-up time

Clock source from HXTAL

33.2

Clock source from IRC8M

31.8

(1)

Based on characterization, not tested in production.

(2)

After power-up, the start-up time is the time between the rising edge of NRST high and the main function.

(3)

PLL is off.

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