GD32F310 datasheet(38/81 Pages) GIGADEVICE

38 / 81 page

GD32F310xx Datasheet



Calendar with subsecond, seconds, minutes, hours, week day, date, year and month

automatically correction



Alarm function with wake up from deep-sleep and standby mode capability



On-the-fly correction for synchronization with master clock. Digital calibration with 0.954

ppm resolution for compensation of quartz crystal inaccuracy.

The real time clock is an independent timer which provides a set of continuously running

counters in backup registers to provide a real calendar function, and provides an alarm

interrupt or an expected interrupt. It is not reset by a system or power reset, or when the

device wakes up from standby mode. In the RTC unit, there are two prescalers used for

implementing the calendar and other functions. One prescaler is a 7-bit asynchronous

prescaler and the other is a 15-bit synchronous prescaler.

3.11

Inter-integrated circuit (I2C)



Up to two I2C bus interfaces can support both master and slave mode with a frequency

up to 1 MHz (Fast mode plus)



Provide arbitration function, optional PEC (packet error checking) generation and

checking



Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface

which is an industry standard two line serial interface used for connection to external

hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line

(SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode,

up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also

has an arbitration detect function to prevent the situation where more than one master

attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided

in I2C interface to perform packet error checking for I2C data.

3.12

Serial peripheral interface (SPI)



Up to two SPI interfaces with a frequency of up to 18 MHz



Support both master and slave mode



Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO

& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by

the DMA controller. The SPI interface may be used for a variety of purposes, including simplex

synchronous transfers on two lines with a possible bidirectional data line or reliable

communication using CRC checking.

GD32F310 数据表(PDF) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

GD32F310 数据表(HTML) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载